Miscellaneous active electrical nonlinear devices – circuits – and – Gating – Utilizing three or more electrode solid-state device
Reexamination Certificate
2003-02-04
2004-02-24
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Gating
Utilizing three or more electrode solid-state device
C327S538000, C327S362000, C323S315000
Reexamination Certificate
active
06696881
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to CMOS circuits and, more particularly, to compensation for gate current leakage in CMOS circuits.
BACKGROUND OF THE INVENTION
It is common practice to use the existing oxide layer as a dielectric for making a PMOS device into a capacitor. A typical configuration for making a PMOS device into a capacitor is to connect the source and the drain, also collectively called diffusions in this configuration, and the N-well tie to a first supply voltage, typically Vdd. The gate is then connected to the desired node, which is typically coupled to other devices such as a filter in a Phase-Locked-Loop (PLL) application. Typically, the desired node has a more negative potential on it than the potential on the source and the drain, i.e., the diffusions.
In this capacitor configuration of a PMOS device, there is a minute, typically negligible in the prior art, DC current flowing from the source and drain, i.e., the diffusions, through the oxide layer of the device to the gate terminal. This DC current flowing from the source and the drain to the gate is a parasitic current known to those of skill in the art as “gate current”.
In the prior art, the thickness of the oxide layer making up the gate was large enough that the gate current was minimal and considered negligible and, therefore, was often ignored, however, to accommodate smaller feature sizes, faster clock speeds and advances in low power circuits, the thickness of gate oxide layers has been steadily decreasing. Indeed, at the time of this application gate oxide layer thickness is approaching 20 angstroms and will soon be even thinner. Consequently, the ability of the gate oxide layer to insulate, and thereby keep the gate current minimal, is constantly decreasing. As a result, in the current electronics design industry, gate current can no longer be, and no longer is, considered negligible.
Unfortunately, gate current may vary as an exponential function of the voltage between the gate and the source (Vgs) of the PMOS device. In addition, when the PMOS device is configured as a capacitor, i.e., the oxide layer is used as the dielectric of a capacitor, it is particularly difficult to compensate for gate current because the gate must remain a “floating node” for an extended period of time and therefore cannot be driven by any external voltage source to create a corrective biasing Vgs.
Gate current is particularly problematic when the PMOS device, configured as a capacitor as discussed above, is used as a filter capacitor in a PLL. Some prior art solutions have been attempted to solve the problem of gate current, however, these solutions: tended to significantly change the characteristics of the capacitor, and therefore affect the efficiency and operational parameters; were often based on the use of non-standard, ultra precise custom components; and/or required a prohibitively large number of additional components.
For instance, prior art “work around” solutions included reducing the operational range of the capacitor or changing the diffusion and well voltage potentials to match the gate potential. Another prior art “solution to the gate current problem was to use two identical capacitors, each having one-half the capacitance of the active capacitor. According to this prior art “solution”, one capacitor was configured like the active capacitor and the other capacitor was connected to the floating node while the poly layer was connected to the second supply voltage, Vss. The thought behind this prior art “solution” was to drain off a current equal to the gate leakage current. However, two capacitors rarely have identical characteristics and prior art this “solution” required three capacitors.
As discussed above, the prior art “solutions” shown above tended to significantly change the characteristics of the capacitor, and therefore affect the efficiency and operational parameters of the filter, were based on the use of non-standard, ultra precise custom components, and/or required a significant number of additional components. Consequently, the prior art “solutions” were, at best flawed work arounds that failed to effectively address the problem of gate current discussed above. Therefore, in the prior art, either the gate oxide layer thickness was increased, a very costly and undesirable option, or gate current was simply assumed and designed around.
What is needed is a method and apparatus for compensating for gate current that does not significantly change the characteristics of the capacitor, uses standard components, requires a minimal number of additional components and is fully independent of process, supply voltage and temperature variations.
SUMMARY OF THE INVENTION
The present invention is directed to a method and apparatus for compensating for gate current through a capacitor. According to the invention, a first capacitor, in one embodiment of the invention a PMOS device configured as a capacitor, has a parasitic DC gate current “Ig”. According to the present invention, gate current Ig is compensated for by a compensation circuit.
In one embodiment of the invention, the compensation circuit includes: a biasing circuit; a first compensation transistor; a second compensation transistor; and a compensation capacitor, in one embodiment of the invention a PMOS device configured as a compensation capacitor.
According to the invention, one purpose of the biasing circuit is to ensure the bias voltage across the compensation capacitor is equal to the bias voltage across the first capacitor. Since, according to the method and apparatus of the present invention, the bias voltages of the first capacitor and the compensation capacitor are kept the same, the gate current Ig of the first capacitor is proportional to the area of the first capacitor and the gate current of the compensation capacitor is proportional to the area of the compensation capacitor.
In addition, according to the invention, the size of the second compensation transistor is chosen such that if, the ratio of the area of the compensation capacitor divided by the area of the first capacitor is area ratio “AR”, then, the ratio of the size of first compensation transistor divided by the size of second compensation transistor is also area ratio “AR”.
According to the invention, when: the first capacitor; the compensation capacitor; the first compensation transistor; and the second compensation transistor are chosen to have the same area ratio “AR” as defined above, then, the gate current Ig, through the first capacitor is equal to the gate current through the compensation capacitor divided by the area ratio “AR” and current through the second compensation transistor is equal to the current through first compensation transistor divided by the area ratio “AR”. Consequently, according to the method and apparatus of the present invention, the gate current Ig through the first capacitor is equal to the current drained off through the second compensation transistor. Therefore, the potentially adverse effects of the gate current Ig through the first capacitor are neutralized by the current drained off through second compensation transistor.
Using the method and apparatus of the present invention, gate current is compensated for without changing the characteristics of the capacitor and by using standard components. In addition, the method and apparatus of the present invention requires a minimal number of additional components and is fully independent of process, supply voltage and temperature variations.
It is to be understood that both the foregoing general description and following detailed description are intended only to exemplify and explain the invention as claimed.
REFERENCES:
patent: 5521490 (1996-05-01), Manohar
patent: 6255897 (2001-07-01), Klemmer
patent: 6617835 (2003-09-01), Nishimura
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Nguyen Long
Sun Microsystems Inc.
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