Oscillators – Solid state active element oscillator – Transistors
Reexamination Certificate
1999-05-03
2001-07-31
Mis, David (Department: 2817)
Oscillators
Solid state active element oscillator
Transistors
C331S034000, C331S17700V, C331S17700V, C331S179000
Reexamination Certificate
active
06268778
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit devices, and more particularly to a method and apparatus for fully integrating a Voltage Controlled Oscillator (VCO) on an Integrated Circuit (IC) device.
2. Description of Related Art
One well-known problem to those skilled in the art of the design and manufacture of integrated circuits is the poor tolerance values associated with integrated circuit components, especially the tolerance values of passive circuit components. Due to process variations, device parameter spread, variations in critical parameters such as conductive layer sheet resistance values, film thickness, process uniformity and manufacturing equipment cleanliness, and other factors, integrated circuit passive electrical components often have tolerances that are approximately an order of magnitude worse than their analogous discrete external passive electrical components. Consequently, it has proven difficult and costly in the past to implement tuned networks or circuits using on-chip passive electrical components. One such tuned circuit is a voltage-controlled oscillator (VCO) in which a number of passive electrical devices are typically utilized to establish both the operating frequency and frequency offset of the VCO.
One well-known solution to this tolerance problem is to “trim” the integrated circuit until it operates within a set of pre-defined post-fabrication parameters. These “post-fabrication trimming” techniques are performed after manufacturing and testing the integrated circuit and are designed to physically alter the integrated circuit using a variety of methods including “Zener-zapping”, laser trimming and fuse trimming. For example, using well-known fuse trimming techniques, fuseable links in an integrated circuit can be blown until the integrated circuit performs adequately under selected nominal conditions. Using these post-fabrication trimming techniques, passive electrical devices can be “fine-tuned” until they have acceptable tolerance values under nominal conditions. Disadvantageously, the trimming techniques produce only static solutions. For example, in fuse trimming, although the devices may perform adequately under nominal conditions, they may not perform adequately under all of the operating conditions of the integrated circuit. However, disadvantageously, the integrated circuit is permanently configured once the fuses are blown.
For example, as the voltage and temperature of the integrated circuit varies over time, offsets can be introduced despite the static settings created during the fuse trimming process. Devices that were once usable under the nominal conditions at which the fuses were blown may become unusable under some operating conditions, thus adversely affecting yield characteristics of the integrated circuits. In addition, the prior art post-fabrication solutions disadvantageously introduce additional manufacturing and testing steps into the manufacturing process. Using these prior art approaches, the manufacturer must first measure performance characteristics, trim the integrated circuits to conform to a selected set of performance and tolerance criteria, and test the results to ensure that the integrated circuit is trimmed appropriately. Thus, the prior art post-fabrication trimming techniques add additional time to the design and fabrication of integrated circuit devices and consequently add to the manufacturing costs of the integrated circuits.
In addition, as is well known in the electrical engineering arts, a voltage-controlled oscillator typically comprises a LC-resonator circuit coupled to an amplifier circuit and a current source. As is well known, the center output frequency f
0
is determined by the values of the inductor L and the total capacitance C of the LC-resonator circuit. More specifically, the center output frequency f
0
generated by the VCO is determined as follows: f
0
is approximately equal to: 1/(2&pgr;*SQRT (L*C
tot
). The value of L is fixed. However, the value of C
tot
is variable and is determined by the capacitance of a tuning varactor that is typically controlled by a tuning voltage of V
tune
. In practice, the VCO is tuned so that the center output frequency f
0
is nominally equal to a desired center frequency, for example, 2 GHz. Disadvantageously, when the VCO is implemented in an integrated circuit, poor tolerance values due to IC fabrication process variations and other factors can adversely affect the previously tuned center frequency. Consequently, the prior art VCO integrated circuit implementations disadvantageously require calibration to re-center the LC-resonator circuit's resonance frequency to a desired center frequency value. Due to variations from part to part, the prior art IC VCO implementations may be unreliable and totally unusable, especially when operating at high frequencies.
This limitation in the prior art IC VCO implementations also disadvantageously limits the frequency range over which the VCO can be tuned (the VCO tuning range). The tuning range of a VCO is determined by the sensitivity of the VCO (measured in Hz/Volt) and the range of the tuning voltage V
tune
that can be applied to the VCO (measured in Volts). For example, a VCO having a sensitivity of 50 MHz/Volt and a tuning voltage range of 2 volts theoretically has a tuning range of 100 MHz. However, due to process variations and other factors, the tuning ranges of the prior art IC VCO implementations are limited even further. Because the center output frequency f
0
varies from part to part as described above, the tuning range of the VCO may be narrowed by as much as 20-30%. Therefore a need exists for a fully integrated VCO that has a reliable and consistent center output frequency (consistent from part to part), is tunable over a wide range of frequencies, and is capable of being calibrated when the center output frequency varies due to process variations.
In addition to variations in desired center frequencies, the prior art IC VCO implementations disadvantageously are also very sensitive to low frequency noise that is introduced into the IC substrate. This sensitivity to noise characteristic not only further limits the prior art VCO tuning ranges, but it also severely limits the utility of the prior art VCO designs in some important applications, such as use in a mixed signal (analog and digital) integrated circuit environment. In general, VCOs are sensitive to noise because they have very high gains and therefore amplify whatever noise is present in the circuit. Most prior art IC VCO designs have been implemented using “junction-isolated” CMOS “bulk” processes wherein a diode-type junction exists between the epitaxial (EPI) silicon layer (“bulk” or “well” wherein specific IC devices are implemented) and the substrate of the device. The capacitance of the well-substrate junction often exhibits a voltage dependency and it is therefore non-linear.
This non-linear well-substrate junction capacitance is particularly problematic in IC VCO implementations. The non-linear well-substrate junction capacitance acts as an undesirable additional tuning port of the VCO. In addition to the desired VCO tuning varactor (controlled by the tuning voltage V
tune
), the well-substrate junction functions as an additional tuning varactor. Disadvantageously, the well-substrate nonlinear capacitance FM-modulates the VCO center output frequency f
0
when low frequency noise is introduced into the substrate. The low frequency noise travels through the substrate and changes the capacitance of the well-substrate junction, which in turn modulates the center output frequency f
0
of the VCO (because the center output frequency is dependent upon the total capacitance of the LC-resonator circuit as described above). Furthermore, due to the well-substrate junction of prior art designs, the total parasitic capacitance is also increased. Increased parasitic capacitance disadvantageously also decreases the tuning range of the IC VCO implementations.
Consequently, due to the well-s
Hull Christopher Dennis
Jansson Lars Gustaf
Mucke Lars Henrik
Jaquez Martin J.
Jaquez & Associates
Mis David
Silicon Wave Inc.
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