Method and apparatus for fractional-N synthesis

Telecommunications – Receiver or analog modulated signal frequency converter – Local control of receiver operation

Reexamination Certificate

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C455S165100

Reexamination Certificate

active

10015993

ABSTRACT:
A method and apparatus for fractional-N synthesis includes processing that begins by generating a 1stfeedback frequency from the output frequency based on a fixed divider value. The processing continues by generating a 2ndfeedback frequency from the output frequency based on a selectable divider value, a modified fractional value of the divider value, and a modified integer value of the divider value. The processing continues by determining whether the fractional value of the divider value is within a range of fractional values. If so, the 1stfeedback frequency is used to produce the output. If the fractional portion of the divider value is not within the range of fractional values, the 2ndfeedback frequency is used to produce the output frequency.

REFERENCES:
patent: 5187722 (1993-02-01), Petty
patent: 5774023 (1998-06-01), Irwin
patent: 7092675 (2006-08-01), Lim et al.
patent: 2002/0121938 (2002-09-01), Fan
“A 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5Mb/s GFSK Modulation”, Michael H. Perrott, Student Member, IEEE, Theodore L. Tewksbury III, Member, IEEE, and Charles G. Sodini, Fellow, IEEE—IEEE Journal of Solid-State Circuits, vol. 32, No. 12, Dec. 1997.

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