Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Radiation or energy treatment modifying properties of...
Reexamination Certificate
2000-11-09
2002-07-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Radiation or energy treatment modifying properties of...
C438S369000, C438S795000
Reexamination Certificate
active
06423605
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for forming an ultra-shallow junction in semiconductor materials by which there can be obtained an improvement in electrical properties in the areas of sheet resistance, junction and thus, in the performance of the resulting semiconductor device in terms of drive current, of state leakage and the punch-through characteristics due to drain—induced barrier lowering (DIBL) The invention also relates to the semiconductor devices so formed.
BACKGROUND OF THE INVENTION
Crystal materials are formed in semiconductor wafers by the selective introduction of dopant atoms into the lattice structure of the semiconductor material and ion implantation has become a widely used and the most appropriate technique for this. In this technique a semiconductor material is bombarded in a vacuum with accelerated ions of a dopant element. These energetic ions penetrate the semiconductor crystal lattice, and come to rest after losing their energy through nuclear and electronic stopping.
During the ion implantation process the semiconductor crystal lattice is damaged and it is necessary to anneal out this damage before further semi-conductor processing can be effected. Therefore following ion implantation, the semiconductor material is annealed to eliminate crystal defects in the diffused layers and to activate the dopant atoms by putting them on substitutional sites. Annealing involves heating the semiconductor material. Conventionally this is done by maintaining the semiconductor material at an elevated temperature, e.g. 900 degrees to 1100 degrees Centigrade. Such a process is of course time consuming and limits the throughput rate. Further, the high temperatures and extended times involved can lead to undesirable diffusion of the dopant. As a result of such diffusion, annealing increases junction depths. Also, thermally activated processes limit the active doping concentration to the solid solubility limit, and hence cause the sheet resistance values to be too high.
The semiconductor industry is moving toward smaller, higher speed devices. One of the conditions for achieving these is limiting the junction depths to less than one micron and better yet if it will be on the order of a few hundred Angstroms or less. Shallow junctions cause less DIBL as channel lengths are scaled down. This allows achieving higher speed and higher integration density as well as reducing short channel effects.
There are different ways to accomplish shallow junctions. The first and most common way is by using low-energy implants combined with rapid thermal annealing (RTA) or other schemes, which minimizes the time and temperature of thermal processing. Usually this is accomplished by using for a selected short time such heat sources as lasers (U.S. Pat. No. 5,399,506), light (U.S. Pat. No. 4,729,962), infrared (U.S. Pat. No. 6,069,062), Xenon and arc lamps (U.S. Pat. Nos. 4,350,537 and 4,331,485), plasma (U.S. Pat. No. 5,672,541), as well as using low frequency (0.9-2.45 GHz) microwave (U.S. Pat. No. 4,667,076). In this case of RTA, there is transient enhanced diffusion (TED) of dopants such as B due to the coupling of B with point defects such as neutral (and charged) Si interstitials which may be released from extended defects such as dislocation loops and rod-like defects. Rapid and multi-stage heating (U.S. Pat. No. 5,773,337) approaches allow reducing the junction depth but not much because the same heating process is used to accomplish both of the main goals: removing crystal damage to the semiconductor material and activating dopants. Optimally these processes require different conditions.
This contradiction is the main problem because it is impossible to separate heating (heat parameters such as temperature and time) of dopant for activation, and lattice for recrystallization (in the case of solid phase epitaxy of amorphous layers), in cases when such heat sources as infrared, laser, light, and other non-selective heaters are used. U.S. Pat. No. 5,395,794 describes activation of the impurity ions by electromagnetic energy radiation with a frequency substantially equal to the resonance frequency of the interstitial impurity ions in the semiconductor material (selective activation). Microwave excitation of an appropriate frequency may break up or prevent the formation of such B-interstitial complexes, thereby minimizing TED, and reducing junction depths. Furthermore, non-thermal microwave excitation may allow the substitutional B concentration to exceed the thermodynamic solid solubility limit, thus reducing sheet resistance. The ions are excited and are raised to an energy level in accordance with the intensity of the electric field of the incident electromagnetic wave. There is a problem with this method in conducting the other important process: removing crystal damage to the semiconductor material that requires heating the lattice to a particular temperature for a certain time (i.e. thermal budget). Because the intensity of the electric field of the incident electromagnetic wave is fixed for the dopant activation process there is no room for selecting the lattice heating level (temperature) that also depends on the level of the electric field (on microwave power). Power must be increased because semiconductor materials are low absorbers of microwave energy. However, increasing the power to achieve the required lattice temperature can cause increasing ion diffusion and as a result, increase the junction depths.
None of the art known to the applicant has provided a satisfactory process for fabricating ultra-shallow junctions of selected junction depth and sheet resistance, particularly where the required junction depth cannot be obtained simply by reducing the implant energy and thermal budget. Accordingly, a need exists for improved methods for fabricating ultra-shallow junctions in semiconductor materials and for improved methods for activating implanted dopants in semiconductor materials by thermal processing.
BRIEF SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to overcome the above problems encountered in the art and to provide a method for forming ultra-shallow junctions of semiconductor materials, whereby their electrical properties (sheet and contact resistance), and their barrier structures can be improved and thus the properties and reliability of the resulting semiconductor device can also be improved in the areas of drive current, off-state leakage punch-through behavior and hot carrier reliability.
In accordance with the present invention, there is provided a method for forming an ultra-shallow junction in a semiconductor material having a lattice and implanted impurity ions having a resonance frequency, comprising an initial rapid heating process using a heat source at a selected temperature and time sufficient to eliminate lattice defects without significant diffusion of the dopants and then exposing the semiconductor materials to electromagnetic radiation. The radiation has a frequency approximately within a range of the resonance frequency of the interstitial impurity ions in the semiconductor material and an electric field intensity range that does not appreciably exceed an activation barrier potential of these interstitial impurity ions.
In a further embodiment of the invention, there is provided a method of forming an ultra shallow junction dopant region in semiconductor substrate having a lattice structure. The method comprises forming the dopant region in the substrate to a depth of less than about one micron, wherein the dopant region includes interstitial impurities in the substrate lattice. The substrate is then heated to reduce lattice defects without producing substantial diffusion of the implanted impurities within the substrate. The implanted impurities are selectively excited without substantially heating the surrounding material of the substrate, so as to cause the impurities to move to substitutional positions within the lattice structure, or alternatively, the substrate is exposed to elec
Shevelev Michael
Sklyarevich Vladislav
Dickstein , Shapiro, Morin & Oshinsky, LLP
Gyrotron Technology, Inc.
Lindsay Jr. Walter L.
Niebling John F.
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