Boots – shoes – and leggings
Patent
1995-09-28
1998-08-25
Teska, Kevin J.
Boots, shoes, and leggings
364491, 257774, G06F 1750
Patent
active
057989370
ABSTRACT:
A method for forming one or more redundant vias (38a-38x) around a critical via (36) involves providing an integrated circuit design file (12) containing several overlay layers. Critical vias in the file (12) are identified via a step (16). Several redundant vias are serially placed around and connected in parallel to the critical via (36), and design rules are checked for each redundant via by performing steps (24-30). Redundant vias which do not violate design rules (26) are kept in a separate redundant overlay layer and added to the design of the integrated circuit. The added redundant vias increase the yield of the integrated circuit by bolstering the integrity of critical via connections.
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Cheng et al, Multi-Level Logic Optimization by Reducing Addition and Removal pp. 373-377.
Michalka et al, A Redundant Metal-Polymide Thin Film Interconnect Process for Wafer Scale Dimensions, pp. 158-164.
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Michalka et al, "A Redundant Meta-Polymide Thin Film Interconnection Process for Wafer Scale Dimensions", 1990.
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New Riverside University Dictionary, Webster, 1994, p. 987, Houghton Mifflin Company, Jan. 1994.
Algor Ilan
Bracha Gabriel
Volpert Yehuda
Weissberger Eytan
Motorola Inc.
Teska Kevin J.
Walker Tyrone V.
Witek Keith E.
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