Coating processes – Electrical product produced – Welding electrode
Patent
1984-09-17
1987-01-13
Lusignan, Michael R.
Coating processes
Electrical product produced
Welding electrode
219121LC, 219121LM, 427 86, 427 88, B05D 306, B05D 512, B23K 900
Patent
active
046364048
ABSTRACT:
A method and apparatus for reliably forming low resistance links between two aluminum conductors deposited on an insulating polysilicon or amorphous silicon layer, employ a laser to bridge a lateral gap between the conductors. The apparatus and method are ideally suited for implementing defect avoidance using redundancy in large random access memories and in complex VLSI circuits. Only a single level of metal is employed and leads to both higher density and lower capacitance in comparison to prior techniques. Resistances in the range of one to ten ohms can be achieved for gap widths of approximately two to three microns.
REFERENCES:
patent: 4023005 (1977-05-01), Bolin
patent: 4151545 (1979-04-01), Schnepf et al.
patent: 4168444 (1979-09-01), van Santen
patent: 4270137 (1981-05-01), Coe
patent: 4270960 (1981-06-01), Bollen et al.
patent: 4289834 (1981-09-01), Alcorn et al.
patent: 4413272 (1983-11-01), Mochizuki et al.
patent: 4438450 (1984-03-01), Sheng et al.
patent: 4446613 (1984-05-01), Beinglass et al.
J. G. Posa, "Redundancy-What to do When the Bits Go Out", 7/28/81, pp. 117-120, Electronics.
G. H. Chapman et al., "A Laser Linking Process for Restructurable VLSI*", MIT, Cleo '82, 4/14-16/82, Phoenix, Arizona.
J. F. Smith et al., "Laser Induced Personalization & Alterations of LSI & VLSI Circuits", IBM Corporation.
O. Minato et al., "A High-Speed Hi-CMOSII 4K Static RAM", pp. 449-453, IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981.
J. M. Harris et al., "Solid-Phase Crystallization of Si Films in Contact with Al Layers*, pp. 2897-2904, Journal of Applied Physics, vol. 48, No. 7, Jul. 1977.
M. Hongo et al., "THD2 Connecting Conductors on Semiconductor Devices by Lasers" Hitachi, Ltd., 4/15/82.
J. I. Raffel et al., "Laser Programmed Vias for Restructurable VLSI*", pp. 132-135, Int'l Electron Devices Meeting, 12/1980.
Chapman Glenn H.
Raffel Jack I.
Yasaitis John A.
Lusignan Michael R.
Mass. Institute of Technology
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