Facsimile and static presentation processing – Static presentation processing – Dot matrix array
Reexamination Certificate
2000-02-25
2003-01-21
Wallerson, Mark (Department: 2622)
Facsimile and static presentation processing
Static presentation processing
Dot matrix array
C358S001160, C358S001170, C358S443000, C358S444000
Reexamination Certificate
active
06509978
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to image processing and more particularly to a method and apparatus for formatting bitmapped data for a printer, such as an inkjet printer.
It is well known to format bitmapped image data for output by a printer, such as an inkjet printer, that scans one or more printing heads over a print medium such as a sheet of paper. Each head can include plural nozzles, i.e. ink orifices, to allow color printing by printing dots of different colors in proximity to, or on top of, one another. For example, if the “CMYK” model is used, orifices for each of the colors cyan, magenta, yellow and black are used in combination to make various colors. The words “bitmap” and “bitmapped” as used herein refer to a representation, consisting of rows and columns of dots, of a graphics image in computer memory. To display a bitmapped image on a monitor or to print it on a printer, the computer formats the bitmapped data into pixels (for display screens) or ink dots (for printers).
During formatting, the bitmapped image data may be subjected to “pixel swath extraction” in which the pixels (i.e., ink dots) are ordered to be associated with a particular print head. Also, the bitmapped image data may be subjected to “nozzle data rendering” in which inkjet nozzle drop data is created based on gray scale data or color gamut data. Pixel swath extraction and nozzle data rendering is ordinarily accomplished by an image processor which reads the bitmapped image out of a memory and formats the data in a known manner. Additionally, the image processor can accomplish error correction and diagnostics based on instructions from the computer generating the image data.
FIG. 2
illustrates a conventional bitmapped image data formatting apparatus. Ordinarily the apparatus is in the physical form of an expansion card that can fit into a slot defined in a computer to interface with a communications bus of the computer. For example, the apparatus can be of a form factor that fits into a PCI (peripheral component interconnect) slot to interface with a personal computer having a PCI bus. Formatting apparatus
10
includes bus interface
12
which includes hardware and/or software to for interfacing with bus
14
of the computer in a known manner. For example bus interface
12
can be a standard PCI interface. Image processor
16
is coupled to bus interface
12
by local communications bus
13
to obtain bitmapped image data output by the computer and to obtain processing instructions from the computer, such as correction instructions and diagnostics, through bus interface
12
. After being formatted by processor
16
, the image data is sent to print interface
18
in a known manner. Interface
18
is associated with one or plural print heads or print engines of the printer (not illustrated) and outputs data for the print heads or print engines in an appropriate protocol, such as Centronix serial, USB (universal serial bus), parallel, or the like, depending on the interface of the printer.
Since a single bus interface and a single local communications bus is used to carry both image data and processing instructions, the processor will have many wait states while it waits for image data to be communicated. Further, the architecture in which a plurality of elements (e.g. the bus interface, the processor, and any buffers, accumulators, or other elements (not illustrated) are disposed in a single data path, presents a high capacitance of the system. Both of these factors serve to slow down the effective formatting speed of the conventional apparatus and cause the computer user to wait. Accordingly, it is desirable to speed up formatting of bitmapped image data for printing.
BRIEF SUMMARY OF THE INVENTION
A first aspect of the invention is an apparatus for formatting bitmapped image data for printing, comprising an image data bus section having an image bus interface adapted to be coupled to a computer bus to transmit the image data, a front end memory coupled to the image bus interface to receive the image data in an unformatted form, a back end memory for receiving the image data in a formatted form, and a print device coupled to the back end memory for transmitting print data based on the image data in a formatted form. The apparatus also comprises a processor bus section having an image processor, a processor bus interface adapted to be coupled to the computer bus to communicate print processing instructions between the print processor and the computer, and a gateway coupling the print processor to the front end memory and the back end memory. The print processor receives the image data in an unformatted form from the front end memory, formats the image data, and transmits the image data in a formatted form to the back end memory.
A second aspect of the invention is a method for formatting bitmapped image data comprising the steps of transmitting the image data through an image bus interface coupled to a computer bus to a front end memory coupled to the image bus interface to store the image data in an unformatted form, communicating print processing instructions, through a processor bus interface coupled to the computer bus, to a print processor, reading the image data in the unformatted form out of the front end memory to the print processor through a gateway coupling the print processor to the front end memory, formatting the image data with the print process or, transferring the image data in a formatted form to a back end memory, and reading the image data in a formatted form out of the back end memory to a print interface device.
Accordingly, the invention provides a processor architecture in which the data and processor address signals are separated. Also, the invention provides a bus structure in which I/O wait states of the most utilized operations, such as instruction fetches from memory and stack variable access from memory, are minimized. The invention also provides the image data its own path as much as possible during formatting and provides concurrent operation of the processor and transfer of image data from the computer.
REFERENCES:
patent: 4562537 (1985-12-01), Barnett et al.
patent: 4648045 (1987-03-01), Demetrescu
patent: 5237655 (1993-08-01), Statt et al.
patent: 5262875 (1993-11-01), Mincer et al.
patent: 5276799 (1994-01-01), Rivshin
patent: 5689313 (1997-11-01), Sotheran
patent: 5740388 (1998-04-01), Hunt
Eastman Kodak Company
Rushefsky Norman
Wallerson Mark
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