Method and apparatus for floating point operation

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G06F 738

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active

048706086

ABSTRACT:
Method and apparatus for floating point operation for calculating an approximate solution in a given argument of a function. An operation unit for carrying out floating point logical operation and floating point multiplication, a first memory for storing data necessary for operation and data produced in a course of operation, a second memory for storing a microprogram for controlling a process of operation of the operation unit, a micro-sequencer for issuing a control command necessary for the operation unit to carry out the operation, in accordance with the microprogram, a third memory for storing a table of solutions of coefficient functions in the series polynomial approximate equation of the function including a coefficient function consisting of numeric logic operation or multiplication operation, and an address latch for designating an address of the solution of the series expansion corresponding to the given argument of the function in the third memory are provided. When the function is instructed and the corresponding argument are given, the micro-sequencer calculates the address in the table of solution of the coefficient function corresponding to the argument, loads the calculated address to the address latch and reads the solution of the coefficient function from the table and supplies it to the operation unit. The operation unit calculates the solution of the given argument of the function based on the solution of the coefficient function read from the table, in accordance with the control command from the micro-sequencer.

REFERENCES:
patent: 4031370 (1977-06-01), Catherall
patent: 4351025 (1982-09-01), Hall, Jr.
patent: 4700319 (1987-10-01), Steiner

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