Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2003-05-12
2004-09-07
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S057000, C702S065000, C702S117000, C702S119000, C702S124000, C702S183000
Reexamination Certificate
active
06789027
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of computers and computer systems. More particularly, the present invention relates to a method and apparatus for a low voltage detection and lockout protection in a flash electrically erasable programmable read only memory array (flash EEPROM).
BACKGROUND OF THE INVENTION
Many of today's computing applications such as cellular phones, digital cameras, and personal computers, use nonvolatile memories to store data or code. Non-volatility is advantageous because it allows the computing system to retain its data and code even when power is removed from the computing system. Thus if the system is turned off or if there is a power failure, there is no loss of code or data.
Nonvolatile semiconductor memory devices are fundamental building blocks in computer system designs. One such nonvolatile memory device is flash memory. Flash memory, also referred to as flash Electrically Erasable Programmable Read-Only Memory (flash EEPROMs) or flash memory, can be programmed by the user, and once programmed, the flash memory retains its data until the memory is erased. Electrical erasure of the flash memory erases the contents of the memory of the device. The flash memory can then be programmed with new code or data. The primary mechanism by which data is stored in flash memory is a flash memory cell.
A flash EEPROM memory device (cell) is a floating gate MOS field effect transistor having a drain region, a source region, a floating gate, and a control gate. Conductors are connected to each drain, source, and control gate for applying signals to the transistor. A flash EEPROM cell is capable of functioning in the manner of a normal EEPROM cell and will retain a programmed value when power is removed from the circuitry. A flash EEPROM cell may typically be used to store a one or zero condition. If multilevel cell (MLC) technology is used, multiple bits of data may be stored in each flash EEPROM cell. Unlike a typical EEPROM cell, a flash EEPROM cell is electrically erasable in place and does not need to be removed and diffused with ultraviolet to accomplish erasure of the memory cells.
Arrays of such flash EEPROM memory cells have been used in computers and similar circuitry as both read only memory and as long term storage which may be both read and written. These cells require accurate values of voltage be furnished in order to accomplish programming and reading of the devices. Arrays of flash EEPROM memory devices are typically used for long term storage in portable computers where their lightweight and rapid programming ability offer distinct advantages offer electro-mechanical hard disk drives.
A number of the electronic systems that use flash memories are small portable devices that rely on batteries for power. As new applications emerge, system designers are open to alternative methods of increasing the battery life of these devices by reducing power consumption. However, the tendency has been to reduce the power requirements of such portable computers to make the computers lighter and to increase the length of use between recharging. This has required that the voltage supply potentials available to the flash memory arrays be reduced.
As the product lines moves towards lower power designs, the VCC supply voltage of some flash memories has also moved to lower levels like 1.8 volt. Similarly, the customer specification for the lockout voltage of the part has also moved to lower VCC ranges. The lockout voltage is defined as the voltage level on the VCC supply below which the flash part will lock itself out from performing any user mode algorithms (program/erase) or read.
In conventional prior art products, the VCC lockout detection was implemented by using a flash cell whose threshold voltage was trimmed to the target lockout voltage of the part. The VCC voltage level was sensed by applying the VCC potential to the gate terminal of this flash cell and then waiting for the drain terminal of the flash cell to be pulled to ground, since the source terminal is grounded. This implementation was acceptable for lockout voltages as low as 2.3 volts.
However, in a 1.8 volt flash part, the lockout voltage has moved down to as low as just 1 volt. The flash cell based VCC lockout detection has a number of limitations in this situation. First, erasing a flash cell all the way down to 1 volt can take a long time. The ultraviolet threshold voltage (UV V
t
) of the flash cell in some semiconductor processes can be as high as 3.5 volts. Hence erasing a flash cell from a V
t
of 3.5 volts down to 1 volt instead of a higher voltage can increase the erase time significantly. Second, this prior art scheme can be sensitive to temperature variations. Hence there is a need for a stable VCC lockout detector that could detect low VCC levels of approximately 1 volt and below. Embodiments of the present invention can serve to eliminate the need for a flash cell based VCC level detection.
REFERENCES:
patent: 4975883 (1990-12-01), Baker et al.
patent: 5040088 (1991-08-01), Harrington et al.
patent: 5301161 (1994-04-01), Landgraf et al.
patent: 5420798 (1995-05-01), Lin et al.
patent: 5428566 (1995-06-01), Robinson
patent: 5438549 (1995-08-01), Levy
patent: 5483486 (1996-01-01), Javanifard et al.
patent: 5495453 (1996-02-01), Wociechowski et al.
patent: 5535168 (1996-07-01), Yepez, III et al.
patent: 5559717 (1996-09-01), Tedrow et al.
patent: 5602789 (1997-02-01), Endoh et al.
patent: 5671179 (1997-09-01), Javanifard
patent: 5784314 (1998-07-01), Sali et al.
patent: 5805091 (1998-09-01), Sherry et al.
patent: 5854762 (1998-12-01), Pascucci
patent: 5898634 (1999-04-01), Chevallier
patent: 5912855 (1999-06-01), McLaury
patent: 5946258 (1999-08-01), Evertt et al.
patent: 5956270 (1999-09-01), Shimomura et al.
patent: 5956289 (1999-09-01), Norman et al.
patent: 6028798 (2000-02-01), Roohparvar
patent: 6160755 (2000-12-01), Norman et al.
patent: 6204701 (2001-03-01), Tsay et al.
patent: 6288629 (2001-09-01), Cofino et al.
patent: 411317648 (1999-11-01), None
Guliani Sandeep K.
Javanifard Johnny
Rao Hari M.
Sundaram Rajesh
Intel Corporation
Shah Ami Patel
Tsai Carol S
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