Method and apparatus for field testing field programmable logic

Details Method and apparatus for field testing field programmable logic Method and apparatus for field testing field programmable logic

1993-10-04

1996-01-30

Voeltz, Emanuel T.

Excavating

371 221, G06F 1100

Patent

active

054886120

ABSTRACT:
Disclosed are methods and apparatus for a testing a field programmable logic gate array. In the method the non-volatile gates are set to a testable setting. The programmable logic array is then configured into (1) a pseudo random pattern generator, (2) a multiple input signature register, (3) a signature comparator, and (4) AND-plane and OR-plane logic array areas. A pseudo random set of test pattern vectors is applied to the programmable logic array from the pseudo random pattern generator. The output is captured in the multiple input signature register and compared in the comparator. Finally, individual non-volatile floating gate field effect transistors are selectively set to provide the desired set of sums of products.

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