Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-10-23
2003-11-04
Le, N. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S522000, C324S713000, C324S701000
Reexamination Certificate
active
06642738
ABSTRACT:
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a switched power supply
100
that may be used to provide power to a computer system. Switched power supply
100
includes a power supply
102
, a transformer
104
, a diode
106
, a capacitor
110
, and a field effect transistor (FET)
112
. Transformer
104
in turn includes a primary coil
114
and a secondary coil
116
. The capacitor
110
operates as an output filter. The switched power supply
100
shown in
FIG. 1
may be a portion of a so-called fly back converter that provides power to a computer system.
Switched power supplies of computer systems are monitored to insure that a proper amount of current is provided to the computer systems. Switched power supplies are monitored by measuring the current flowing through the primary coil. The current flow through the primary coil can be monitored by monitoring the current flow I
L
through FET
112
. I
L
can be measured via the voltage V
D
at the drain of FET
112
. More particularly, I
L
can be measured in accordance with the following equation:
I
L
=V
D
/RDSON
(1)
where RDSON represents the source to drain resistance of FET
112
when FET
112
is in the on state. I
L
can be compared against predetermined current values to determine whether I
L
is operating in an acceptable range. For example, I
L
may be compared to I
M
where I
M
represents a maximum limit of the acceptable range of current flowing through FET
112
.
The value of RDSON in equation 1 above can be calculated as follows:
RDSON=RDSON
(
25
)·(1
+AT
) (2)
where RDSON(
25
) represents the resistance of FET
112
between the drain and source at 25° C. when FET
112
operates in the on state, A is a well-known temperature coefficient of RDSON, and T is the temperature measured in centigrade of FET
112
operating in the on state at the time voltage V
S
is compared with the voltage V
M
. Using equation (2), equation (1) can be translated into:
I
L
=V
S
/(
RDSON
(
25
)·(1+
AT
)) (3)
Several problems exist with the prior art method of monitoring current via equation (3) above. The first problem is that the temperature T of FET
112
is difficult to measure. A thermocouple for generating a signal indicative of temperature, could be attached to FET
112
, and the output of the thermocouple could be input into a circuit that generates I
L
as a function of the temperature output of the thermocouple, a calculated value for RDSON(
25
), and V
S
in accordance with equation (3) above. Attaching a thermocouple to FET
112
will be expensive and would give rise to reliability issues. Alternatively, T could be presumed. In other words, a presumption could be made that FET
112
will operate in the on state at a predetermined temperature T
P
. Under this presumption, I
L
could be generated as a function of:
I
L
=V
S
/((
RDSON
(
25
)·(1+
AT
P
)). (4)
If the presumption for T
P
is inaccurate, comparing I
L
to I
M
may not be a reliable means of determining whether current flowing through FET
112
is operating below a predetermined maximum.
The second problem with equation (3) above relates to differences between the actual and calculated values of RDSON(
25
). The actual value of RDSON(
25
) is subject to a statistical distribution. In practice, RDSON(
25
) varies from FET to FET due to fabrication variances. For example, one FET fabricated on a first wafer may have an RDSON(
25
) which differs from that of another FET fabricated on a different part of the wafer or on another wafer. The variances may be due to, for example, variances in doping density. The accuracy of equation (3) is dependent upon how close the actual RDSON(
25
) value is to the calculated value of RDSON(
25
). If the calculated and actual values of RDSON(
25
) differ significantly, than comparing I
L
to I
M
may not be a reliable means of determining whether current flowing through FET
112
is operating below a predetermined maximum.
The temperature dependency of RDSON could be up to 30 to 40% over the span of ambient temperature to max operating temperature. The statistical distribution of RDSON(
25
) due to fabrication variances could be as large as plus or minus 30%. Accordingly, the model above may not lead to an accurate monitoring of current provided by switched power supply
100
SUMMARY OF THE INVENTION
Disclosed is a method and apparatus for FET current sensing using the voltage drop across the drain to source resistance that eliminates dependencies on temperature of the FET and/or statistical distribution of the initial value of drain to source resistance of the FET. In one embodiment, first and second FETs are provided. Each of the first and second FETs include a gate, a source, and a drain. The gate of the first FET is configured to receive a first voltage, and the source of the first FET is configured to be coupled to ground. The gate of the second FET is configured to receive a second voltage, and the source of the second FET is configured to be coupled to ground. A circuit is also provided and includes first and second input nodes coupled to the drains of the first and second FETs, respectively. The circuit is configured to generate a signal as a function of a voltage measured at the drain of the first FET with respect to ground, wherein the signal is proportional to a current flowing into or out of the drain of the first FET.
In one embodiment, the first and second FETs are formed adjacent to each other on a semiconductor wafer ensuring close matching of their electrical characteristics so that the first and second FETs operate in the on state at substantially the same temperature.
In one embodiment, the signal generated by the circuit is proportional to a ratio of substrate areas over which the first and second FETs are respectively formed.
REFERENCES:
patent: 3777577 (1973-12-01), Planey
patent: 4827207 (1989-05-01), Chieli
patent: 4903189 (1990-02-01), Ngo et al.
patent: 5365102 (1994-11-01), Mehrotra et al.
patent: 5612567 (1997-03-01), Baliga
patent: 6177712 (2001-01-01), Miyasaka
patent: 6303969 (2001-10-01), Tan
patent: 6313482 (2001-11-01), Baliga
patent: 406204551 (1997-07-01), None
B. Jayant Baliga, “New Concepts In Power Rectifiers,”Physics of Semiconductor Devices, Proceedings of the Third International Workshop, World Scientific Publishing Co., Singapore, Nov. 27-Dec. 2, 1985, pp. 471-481.
Fairchild Semiconductor Corporation
Le N.
Sidley Austin Brown & Wood LLP
Teresinski John
LandOfFree
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