Method and apparatus for fetching and issuing dual-word or multi

Details Method and apparatus for fetching and issuing dual-word or multi Method and apparatus for fetching and issuing dual-word or multi

1997-04-21

1998-11-10

Lim, Krisna

395381, G06F 922

Patent

active

058357467

ABSTRACT:
An instruction fetch and issuance unit (200) fetches two instruction words and issues at least one instruction word to an instruction decoder (250) per clock cycle. Two multiplexers (220, 230) receive the two fetched instructions and one or both of two of three words stored in an instruction register (240). A controller (210) selectively controls (207-209), in accordance with a state diagram (300), the loading of three words into the instruction register (240) from among the inputs of the multiplexers (220,230). The instruction register (240) issues up to two instructions per clock cycle without requiring the processor to stall to retrieve an additional word, allowing efficient issuance of a double-word instruction or two instructions in parallel.

REFERENCES:
patent: 3629853 (1971-12-01), Newton
patent: 5131086 (1992-07-01), Circello et al.
patent: 5179671 (1993-01-01), Kelly et al.
patent: 5241636 (1993-08-01), Kohn
patent: 5488729 (1996-01-01), Vegesna et al.

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