Method and apparatus for fault tolerance

Details Method and apparatus for fault tolerance Method and apparatus for fault tolerance

1990-06-25

1993-09-07

Beausoliel, Jr., Robert W.

Excavating

371 683, 371 681, 371 19, 395575, H04L 108

Patent

active

052436071

ABSTRACT:
A method and apparatus for achieving fault tolerance in a computer system having at least a first central processing unit and a second central processing unit. The method comprises the steps of first executing a first algorithm in the first central processing unit on input which produces a first output as well as a certification trail. Next, executing a second algorithm in the second central processing unit on the input and on at least a portion of the certification trail which produces a second output. The second algorithm has a faster execution time than the first algorithm for a given input. Then, comparing the first and second outputs such that an error result is produced if the first and second outputs are not the same. The step of executing a first algorithm and the step of executing a second algorithm preferably takes place over essentially the same time period.

REFERENCES:
patent: 4696003 (1987-09-01), Kerr
patent: 4756005 (1988-07-01), Shedd
patent: 5005174 (1991-04-01), Bruckert et al.
H. Geng, "Circuit for the Complete Check of a Data-Processing System", IBM TDB, vol. 16, No. 4, Sep. 1974, pp. 1144-1145.
K. Knowlton, "A Combination Hardware-Software Debugging System," IEEE Transactions on Computers, Jan. 1968, pp. 81-86.

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