Patent
1978-05-15
1979-04-10
Claffy, Kathleen H.
H04J 314
Patent
active
041490380
ABSTRACT:
An idle channel test is provided for a digital time division multiplex and time switching network telecommunications system to detect and diagnose faults in an information path which routes digital information in dedicated channel time slots to and from a "time" switching network. In order to detect and diagnose faults in the information path which includes multiplex/demultiplex circuitry, an idle channel is selected as a test channel at the input to the multiplexer which in turn is the input to the switching network, a test pattern including a bit pattern and a parity bit is inserted into the test channel, the test pattern is connected via the switching network back to one of the demultiplexers and the bit pattern and parity bit are monitored for errors. The idle channel test also allows for the deliberate insertion of a bit pattern error or a parity bit error so the loop from multiplexer, through the switching network and back to any one of a plurality of predetermined demultiplexers can be marked by the propogation of the inserted bit pattern or parity bit error for isolating a fault in the loop.
REFERENCES:
patent: 3686441 (1972-08-01), Thomas
Chaddha Tej N.
Min Byung C.
Pitroda Satyan G.
Claffy Kathleen H.
Kemeny E. S.
Wescom Switching Inc.
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