Patent
1996-03-29
1997-04-08
Harrell, Robert B.
395250, 395465, 395800, G06F 930, G06F 938
Patent
active
056196679
ABSTRACT:
A fast fill method and apparatus for an instruction queue within a pipeline processor is provided. An instruction queue is placed between a translator and an instruction register within a pipeline processor to reduce holes or bubbles in the pipeline resulting from either the fetch stage or the translate/decode stage. The instruction queue is fast filled by the translator by providing multiple micro instructions from the translator, in parallel to either or both of the instruction queue and the instruction register. Queue store control logic is provided to manage sequencing of micro instructions between the translator, the instruction queue, and the instruction register.
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Henry Glenn
Parks Terry
Harrell Robert B.
Huffman James W.
Integrated Device Technology Inc.
Najjar Saleh
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