Method and apparatus for fast fill of translator instruction que

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Details

395250, 395465, 395800, G06F 930, G06F 938

Patent

active

056196679

ABSTRACT:
A fast fill method and apparatus for an instruction queue within a pipeline processor is provided. An instruction queue is placed between a translator and an instruction register within a pipeline processor to reduce holes or bubbles in the pipeline resulting from either the fetch stage or the translate/decode stage. The instruction queue is fast filled by the translator by providing multiple micro instructions from the translator, in parallel to either or both of the instruction queue and the instruction register. Queue store control logic is provided to manage sequencing of micro instructions between the translator, the instruction queue, and the instruction register.

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patent: 5235686 (1993-08-01), Bosshart
patent: 5317701 (1994-05-01), Reininger et al.
patent: 5497496 (1996-03-01), Ando
patent: 5509130 (1996-04-01), Trauben et al.

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