Method and apparatus for fast dependency coordinate matching

Details Method and apparatus for fast dependency coordinate matching Method and apparatus for fast dependency coordinate matching

2005-05-03

2005-05-03

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reexamination Certificate

active

06889314

ABSTRACT:
Disclosed herein is a method for matching dependency coordinates and an efficient apparatus for performing the dependency coordinate matching very quickly. A plurality of buffers to store instructions is set forth. Each storage location of a buffer corresponds to a particular pair of dependency coordinates. Dependency matching logic receives the dependency coordinates for a buffered instruction and scheduling information pertaining to dispatched instructions. The dependency matching logic indicates whether a dependency precludes scheduling of the corresponding buffered instruction. Dependency checking logic produces a ready signal for the buffered instruction when no such dependency is indicated by the dependency matching logic.

REFERENCES:
patent: 5710902 (1998-01-01), Sheaffer et al.
patent: 5787287 (1998-07-01), Bharadwaj
patent: 6016540 (2000-01-01), Zaidi et al.
patent: 6065105 (2000-05-01), Zaidi et al.
patent: 6366993 (2002-04-01), Schrader
patent: 6557095 (2003-04-01), Henstrom

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