Method and apparatus for fast carry generation detection and com

Details Method and apparatus for fast carry generation detection and com Method and apparatus for fast carry generation detection and com

1995-12-22

1998-07-14

Malzahn, David H.

Boots, shoes, and leggings

3401462, G06F 702

Patent

active

057814651

ABSTRACT:
Two binary two's complement numbers X and Y are compared using half-adders and a parallel prefix-and circuit to find a carry bit that results from forming the sum C+S, where C is the carry word and S is the sum word of the half-adder representation of X+Y. The carry bit is used to calculate the sign of C+S and the sign is used to determine whether X<Y, or X>Y. Additionally, the circuit also indicates when X=Y.

REFERENCES:
patent: 4935719 (1990-06-01), McClure
patent: 5281946 (1994-01-01), Le
patent: 5495434 (1996-02-01), Taniguchi
patent: 5592142 (1997-01-01), Adams et al.
"Binary Counter with Counting Period of One Half Adder Independent of Counter Size", Jun. 1989 IEEE, vol. 36, No. 6, pp. 924-926.

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