Dynamic magnetic information storage or retrieval – General processing of a digital signal – Pulse crowding correction
Reexamination Certificate
1996-05-20
2003-05-13
Faber, Alan T. (Department: 2651)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Pulse crowding correction
C360S051000, C360S046000, C360S068000
Reexamination Certificate
active
06563655
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data processing and data storage, and more particularly to precompensation of write data signals.
2. Background Art
Computer systems employ data storage devices, for example, disk drives, to store data for use by the computer system. A typical data storage device includes storage media, in which data is stored, a read head, and a mechanism, such as a motor, for imparting relative motion between the storage media and the read head. The relative motion allows access to various portions of the storage media, and, in the case of certain types of media, such as magnetic media, allows for the production of signals representative of the data stored in the storage media.
In general, disk memories are characterized by the use of one or more magnetic media disks mounted on a spindle assembly and rotated at a high rate of speed. Each disk typically has two surfaces of magnetic media. In a typical rotating medium as a storage system, data is stored on magnetic or magneto-optical disks in a series of concentric “tracks,” with each track being an addressable area of the memory array. A read/write head is provided for each surface of each disk in the disk storage system. These tracks are accessed by read/write head that detects variations in the magnetic orientation of the disk surface.
To provide retrieval of stored data from a storage medium, the fixed representation of the stored data in the storage medium must be converted into signal that may be processed to yield data in a form usable with a system such as a computer system. A read channel circuit is used to convert signals from the storage media to usable read data.
Information is often provided to a read channel in a bit stream format. A bit stream consists of a series of logical ones or zeros presented in serial fashion. To accurately decode a serial bit stream, the read channel must be able to detect each individual bit. To isolate each bit, a bit frame or bit window is defined about each bit. A bit window should only contain a single bit. If the window is too large, more than one bit of information may be contained within the window and one or all bits may be lost. If the bit window is too small, no detectable information will result. Further, loss of bit information at point locations may lead to error propagation throughout the decoding process.
A read channel circuit is used to read data from a storage device, for example a hard disk drive. A read channel circuit typically includes a pulse detector, a filter, servo circuits, a data synchronizer, a window shift circuit, a write precompensation circuit, an encoder/decoder (ENDEC), and a control circuit. The pulse detector detects and qualifies encoded read signals derived from the storage device. The filter further processes the encoded read signals to ensure frequency range and phase relationships of the encoded read signals are appropriate to allow read data to be recovered from the encoded read signals. The servo circuits capture servo information derived from the storage device which is used to assure that data to be read from the storage device has been accurately located.
In the read mode, the data synchronizer performs sync field search and data synchronization. The data synchronizer uses a phase locked loop (PLL) to provide data synchronization and to develop a decode window. The window shift circuit shifts the phase of the voltage controlled oscillator (VCO) of the PLL to effectively shift the relative position of the read data pulse within the decode window. In the write mode, the write precompensation circuit uses the data synchronizer to provide data encoding and independent late/early write precompensation for NRZ data. The ENDEC provides encoding and decoding, preferably of run length limited (RLL) signals. The control circuit coordinates and controls the operation of the aforementioned circuits and subsystems.
A write precompensation circuit provides write precompensation. Write precompensation compensates for media bit shift caused by magnetic nonlinearities. Specific write data patterns are recognized and delays are added in the time position of write data bits to counteract the effects of the magnetic nonlinearities. The magnitude of the time shift required depends on the specific nonlinearities of the particular magnetic media involved. Therefore, the amount of precompensation is typically be made programmable to allow users the flexibility to set the amount needed in specific applications. Pre-compensation is performed only on the second of two consecutive “ones” in a write data stream and shifts the time position of the write data bits in only the late direction. If more than two consecutive “ones” are written in a write data stream, all but the first are precompensated in the late direction.
FIG. 1
is a schematic diagram illustrating a typical write precompensation circuit.
Circuit
101
is a portion of the circuit of FIG.
1
. Circuit
101
comprises transistors
106
,
107
,
111
,
113
,
114
,
117
,
118
,
121
,
122
,
123
,
124
,
128
,
129
,
133
,
134
,
137
,
138
,
139
,
140
,
146
and
147
. Circuit
101
comprises resistors
108
,
109
,
112
,
119
,
120
,
125
,
126
,
127
,
131
,
132
,
136
,
141
,
142
and
148
. Circuit
101
comprises capacitor
115
, current source
130
and variable current source
149
.
The circuit of
FIG. 1
comprises timing generator
102
and comparator
103
. Timing generator
102
comprises transistors
106
,
107
,
111
,
113
,
114
,
117
and
118
. Timing generator
102
comprises resistors
108
,
109
,
112
,
119
and
120
. Timing circuit
102
comprises capacitor
115
. Comparator
103
comprises transistors
133
,
134
,
135
,
137
,
138
,
139
,
140
,
146
and
147
. Comparator
103
comprises resistors
131
,
132
,
136
,
141
,
142
and
148
. Comparator
103
comprises variable current source
149
.
Input CLK at node
104
is coupled to the base of transistor
106
and to the base of transistor
129
. Input CLK* at node
105
is coupled to the base of transistor
107
and to the base of transistor
128
. Positive voltage supply V+ at node
150
is coupled to a first terminal of resistor
108
and to a first terminal of resistor
109
. A second terminal of resistor
108
is coupled to node
152
, at which signal Vno is present, to the collector of transistor
106
and to the base of transistor
114
. A second terminal of resistor
109
is coupled to node
153
, at which signal Vpo is present, to the collector of transistor
107
and to the base of transistor
113
.
Input Vbias at node
110
is coupled to the base of transistor
111
, to the base of transistor
123
, to the base of transistor
124
, to the base of transistor
135
, to the base of transistor
139
and to the base of transistor
140
. The emitter of transistor
111
is coupled to a first terminal of resistor
112
. The second terminal of resistor
112
is coupled to ground at node
151
. The collector of transistor
111
is coupled to the emitter of transistor
106
and to the emitter of transistor
107
.
Positive voltage supply V+ at node
150
is coupled to the collector of transistor
113
and to the collector of transistor
114
. The emitter of transistor
113
is coupled to the base of transistor
122
, to a first terminal of capacitor
115
, to the collector of transistor
117
, and to node
154
, at which signal Vcp is present. The emitter of transistor
114
is coupled to the base of transistor
121
, to the second terminal of capacitor
115
, to the collector of transistor
118
, and to node
155
, at which signal Vcn is present.
Voltage Vc is measured across capacitor
115
, with node
154
being the positive terminal and node
155
being the negative terminal for the purposes of measurement. The emitter of transistor
117
is coupled to a first terminal of resistor
119
. The second terminal of resistor
119
is coupled to ground at node
151
. The emitter of transistor
118
is coupled to a first terminal of
Fukahori Kiyoshi
Ohtsu Tomoaki
Yamasaki Richard G.
Brady W. James
Faber Alan T.
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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