Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2007-10-30
2007-10-30
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S141000, C370S503000
Reexamination Certificate
active
11237276
ABSTRACT:
A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.
REFERENCES:
patent: 4819081 (1989-04-01), Volk et al.
patent: 5266851 (1993-11-01), Nukui
patent: 5432823 (1995-07-01), Basbarro et al.
patent: 5504742 (1996-04-01), Kakuma et al.
patent: 5509038 (1996-04-01), Wicki
patent: 5550875 (1996-08-01), Bennett
patent: 5551050 (1996-08-01), Ehlig et al.
patent: 5646519 (1997-07-01), Hamilton et al.
patent: 5652530 (1997-07-01), Ashuri
patent: 5757868 (1998-05-01), Kelton et al.
patent: 5799048 (1998-08-01), Farjad-Rad et al.
patent: 5909473 (1999-06-01), Aoki et al.
patent: 5923190 (1999-07-01), Yamaguchi
patent: 6008680 (1999-12-01), Kyles et al.
patent: 6100722 (2000-08-01), Dalmia
patent: 6150889 (2000-11-01), Gilliver et al.
patent: 6172540 (2001-01-01), Gandhi
patent: 6205191 (2001-03-01), Portmann et al.
patent: 6233528 (2001-05-01), Lai et al.
patent: 6334163 (2001-12-01), Dreps et al.
patent: 6473439 (2002-10-01), Zerbe et al.
patent: 6614314 (2003-09-01), d'Haene et al.
patent: 6798259 (2004-09-01), Lin
patent: 6799280 (2004-09-01), Edenfield et al.
patent: 6949958 (2005-09-01), Zerbe et al.
patent: 6987823 (2006-01-01), Stark et al.
patent: PCT/US98/21448 (1993-04-01), None
patent: WO93/18463 (1993-09-01), None
patent: WO96/41267 (1996-12-01), None
Dennison, L.R., et al., “Low Latency Plesiochronous Data Retiming,” Artificial Intelligence Laboratory, MIT, date unknown.
Messerschmitt, D.G., “Synchronization in Digital System Design,” IEEE J. on Selected Areas in Communications, vol. 8, No. 8, Oct. 1990.
Abhyankar Abhijit M.
Barth Richard M.
Chan Andy Peng-Pui
Ching Michael Tak-kei
Davis Paul G.
Morgan & Lewis & Bockius, LLP
Nguyen Hai L.
Rambus Inc.
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