Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1997-05-20
2001-03-06
Pham, Chi H. (Department: 2731)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S522000
Reexamination Certificate
active
06198753
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of communication systems and in particular to a method and apparatus for facilitating an interface to a digital signal processor.
BACKGROUND OF THE INVENTION
In modern telecommunication systems, it is often desirable to perform various signal processing functions such as echo cancellation, noise cancellation, and voice enhancement on signals received from telecommunication lines. As such, it becomes necessary to provide an interface between a telecommunication line and a digital signal processor capable of performing such functions.
One function of such an interface is to ensure proper signal synchronization. Incoming signals contain timing and synchronization information which can be distorted or lost during various signal processing functions. To ensure proper system operation, this signaling information must be accurately replaced prior to transmitting the processed signal. One approach to replacing lost signaling information is to insert signaling information into a particular bit of each frame in the signal. A problem with this method arises in T
1
applications, where signaling information resides only in particular frames of the signal. Inserting signaling information into every frame of a T
1
signal results in signal degradation as valid data is overwritten with signaling information. Another approach to replacing lost signaling information is to utilize a digital signal processor containing a synchronization algorithm to define the proper signaling frames. This approach is problematic, however, because adding such an algorithm to the digital signal processor itself would require implementing a myriad of complex logic resulting in increased expense.
In the interest of economy, telecommunication systems are often designed such that several system elements share a single digital signal processor. Where several system elements compete for a single digital signal processor, necessity dictates that the limited processing resources not be wasted by processing incomplete data or idle code. It therefore becomes desirable to detect the presence of incomplete data or idle code in the incoming signal, and to disable the digital signal processor with respect to those signals. In this way, the system's limited processing resources are conserved, leaving more resources available for the processing of incoming signals containing valid data.
One approach to detecting idle code is to compare the incoming signal to a fixed idle code pattern, such as “11111111.” A disadvantage of this method is that fixed idle code patterns offer less system stability than a varied idle code pattern, such as “10101010.” Further, a received signal may contain incomplete information, in other words less information than that originally transmitted. This may occur where the least significant bit of the received signal becomes “stuck” at “0” or “1.” One approach to detecting this condition is to perform frequency analysis on the incoming signal. A disadvantage of this method is that it is complex and expensive to implement.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a telecommunication line-to-digital signal processor interface that provides synchronization of a transmitted processed signal, detects idle code and incomplete data, and facilitates interfaces between a variety of digital signal processor's and communication lines. In accordance with the present invention, an apparatus and method for facilitating an interface to a digital signal processor are provided that substantially eliminate or reduce disadvantages and problems associated with conventional digital signal processor interfaces.
According to one aspect of the present invention, a data path interface for receiving an incoming signal and facilitating an interface to a digital signal processor includes a synchronizer operable to receive a multiframe synchronization signal and to generate a transmitted multiframe synchronization signal in response thereto. The transmitted multiframe synchronization signal determining a signaling frame in a processed signal received from the digital signal processor to reduce signaling noise.
According to another aspect of the present invention, a data path interface for receiving an incoming signal and facilitating an interface to a digital signal processor includes an idle code detector operable to receive an incoming signal and to detect an idle code present in the incoming signal by comparing the incoming signal to at least one user-programmable idle code pattern.
According to yet another aspect of the present invention, a data path interface for receiving an incoming signal and facilitating an interface to a digital signal processor includes a least significant bit detector operable to detect a loss of information in the incoming signal by monitoring the status of the least significant bit of each channel to determine whether it is stuck at a particular value.
According to still another aspect of the present invention, a data path interface for receiving an incoming signal and facilitating an interface to a digital signal processor includes a daughter card interface operable to facilitate an interface to a daughter card. The daughter card interface may include a multiplexer operable to receive and concatenate signals containing N-bit words to form concatenated signals containing 2N-bit words. The daughter card interface being further operable to transmit the concatenated signals to a daughter card.
The present invention provides various technical advantages over conventional digital signal processor interfaces. For example, one technical advantage includes facilitating synchronization of the processed signal by generating a transmitted multiframe synchronization signal. Utilizing the transmitted multiframe synchronization signal reduces signaling noise by defining correct signaling frames in the processed signal. Another technical advantage of the present invention is providing a method of idle code detection based on user-programmable idle code patterns. Implementing user-programmable idle code patterns facilitates the use of varied idle code patterns which offer increased system stability over systems using fixed idle code patterns. Yet another advantage of the present invention is the provision of a simple method of detecting a loss of information in the incoming signal.
Still another advantage of the present invention is facilitating an interface with a daughter card wherein the interface concatenates incoming signals having N-bit words and transmits concatenated signals containing 2N-bit words to the daughter card.
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Kaplan Thomas M.
Virdee Harbhajan S.
Alcatel USA Sourcing L.P.
Baker & Botts L.L.P.
Pham Chi H.
Yao Kwang B.
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