Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-07-05
2003-11-04
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S700000
Reexamination Certificate
active
06642154
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the process of manufacturing structures on a silicon substrate. More specifically, the present invention relates to devices created through a process that uses chemically-selective endpoint detection to fabricate structures on a silicon substrate.
2. Related Art
The dramatic advances in computer system performance during the past 20 years can largely be attributed to improvements in the processes that are used to fabricate integrated circuits. By making use of the latest processes, integrated circuit designers can presently integrate computing systems comprised of hundreds of millions of transistors onto a single semiconductor die which is a fraction of the size of a human fingernail.
This integrated circuit fabrication technology is also being used to fabricate Micro-Electro-Mechanical Systems (MEMs), such as microscopic motors and other types of actuators, that are invisible to the unaided human eye, and which have dimensions measured in fractions of microns.
A typical fabrication process builds structures through successive cycles of layer deposition and subtractive processing, such as etching. As the dimensions of individual circuit elements (or MEMs structures) continues to decrease, it is becoming necessary to more tightly control the etching operation. For example, in a typical etching process, etching is performed for an amount of time that is estimated by taking into account the time to etch through a layer to reach an underlying layer, and the time to overetch into the underlying layer. However, this process can only be controlled to +/−100 Angstroms, which can be a problem in producing Heterojunction Bipolar Transistors (HBTs), in which some layers may only be only hundreds of Angstroms thick.
Furthermore, conventional etching processes that indiscriminately etch all exposed surfaces are not well-suited to manufacture some finely detailed MEMs structures that require tighter control over subtractive processing operations.
What is needed is a process and an apparatus that facilitates selective etching to form a structure on a silicon or other substrate.
SUMMARY
One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.
In one embodiment of the present invention, the etch rate of the first etching operation through the second material is substantially equal to the etch rate of the first etching operation through the first material.
In one embodiment of the present invention, the first etching operation is a reactive ion etch.
In one embodiment of the present invention, receiving the silicon substrate involves receiving the first layer, and depositing the second layer over the first layer. It also involves applying a photoresist layer over the second layer, exposing the photoresist layer through a mask, and developing the exposed photoresist layer. In this way, portions of the photoresist layer defined by the mask are removed, so that corresponding portions of the second layer are uncovered for subsequent etching.
In one embodiment of the present invention, the second layer is an epitaxial layer.
In one embodiment of the present invention, the first material comprises Si—Ge or Si—Ge—C, the second material comprises Si, and the selective etchant comprises KOH.
In one embodiment of the present invention, the first material comprises Si—Ge—C, wherein the carbon is approximately one atomic percent, the second material comprises Si, and the selective etchant is KOH—H
2
O.
In one embodiment of the present invention, the first material comprises Si, the second material comprises Si—Ge or Si—Ge—C, and the selective etchant comprises TMAH or HNA.
In one embodiment of the present invention, the second layer includes one or more silicon and/or polysilicon layers.
In one embodiment of the present invention, the first etching operation and the second etching operation are used to form a Heterojunction Bipolar Transistor.
One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material and an overlying second layer composed of a second material. The process performs a first etching operation that etches through the second layer to the first layer using a selective etchant. The etch rate of the selective etchant through the second material is greater than the etch rate of the selective etchant through the first material, so that the first etching operation etches through the second layer and stops at the first layer. Next, the process performs a second etching operation to overetch into the first layer using a non-selective etching process, such as plasma etching.
REFERENCES:
patent: 5906708 (1999-05-01), Robinson et al.
patent: 5961877 (1999-10-01), Robinson et al.
Hunt Charles E.
Peterson Jeffrey J.
Nelms David
Park Vaughan & Fleming LLP
The Regents of the University of California
Vu David
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