Method and apparatus for fabricating self-aligned contacts...

Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction

Reexamination Certificate

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C257S192000, C257S413000

Reexamination Certificate

active

06974968

ABSTRACT:
An integrated circuit includes a substrate with a gate section projecting upwardly between spaced source and drain regions. Side walls project upwardly beyond the gate section on opposite sides thereof. A dielectric layer has an upper surface spaced above the upper ends of the side walls. Contact openings are created through the dielectric layer, so as to expose surface portions on the source and drain regions. Conductive contacts are formed in the contact openings. The portions of the side walls which project above the gate section permit misalignment of the contact openings, without exposing any portion of the gate electrode during formation of either contact opening.

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Stanley Wolf Silicon Processing for The VSLI Era vol. 2 Lattice Press 1990 p. 280.
U.S. Appl. No. 09/661,735, filed Sep. 14, 2000 by Inventors Theodore W. Houston and Keith A. Joyner, entitled “Semiconductor Device with Fully Self-Aligned Local Interconnects, and Method for Fabricating the Device”.

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