Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of...
Reexamination Certificate
2004-08-17
2009-02-24
Menz, Douglas M (Department: 2891)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
C438S337000, C438S364000, C438S478000
Reexamination Certificate
active
07494887
ABSTRACT:
A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises acts for fabricating a set of extrinsic layers by depositing a highly-doped p+ layer on a substrate, depositing a masking layer on highly-doped p+ layer, patterning the masking layer with a masking opening, removing a portion of the highly-doped p+ layer and the substrate through the masking opening in the masking layer to form a well, and growing an intrinsic layered device in the well by a combination of insitu etching and epitaxial regrowth, where an intrinsic layer has a thickness selected independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have thick extrinsic base layer (low base resistance) and thin intrinsic base layer (short base transit times) simultaneously.
REFERENCES:
patent: 4728624 (1988-03-01), Silvestri et al.
patent: 4746626 (1988-05-01), Eda et al.
patent: 4789643 (1988-12-01), Kajikawa
patent: 4857479 (1989-08-01), McLaughlin et al.
patent: 4896203 (1990-01-01), Kajikawa
patent: 4897704 (1990-01-01), Sakurai
patent: 4920401 (1990-04-01), Sakai et al.
patent: 5111265 (1992-05-01), Tanaka
patent: 5258642 (1993-11-01), Nakamura
patent: 5286997 (1994-02-01), Hill
patent: 5389562 (1995-02-01), Mohammad
patent: 5656514 (1997-08-01), Ahlgren et al.
patent: 5656515 (1997-08-01), Chandrasekhar et al.
patent: 6232649 (2001-05-01), Lee
patent: 6319786 (2001-11-01), Gris
patent: 6410404 (2002-06-01), Zambrano
patent: 6897545 (2005-05-01), Menut et al.
patent: 6972237 (2005-12-01), Verma et al.
patent: 2003/0045066 (2003-03-01), Igarashi
patent: 2005/0017325 (2005-01-01), Gris
W. Liu, et al., “Laterally etched undercut (LEU) technique to reduce base-collector capacitance in heterojunction bipolar transistors,” IEEE GaAs IC Symposium, 1995, pp. 167-170.
M. Rodwell, et al., “Submicron scling of HBT's,” IEEE Trans. Elect. Dev., vol. 48, No. 11, pp. 2406-2624.
HRL Laboratories LLC
Menz Douglas M
Such Matthew W
Tope-McKay & Associates
LandOfFree
Method and apparatus for fabricating heterojunction bipolar... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for fabricating heterojunction bipolar..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for fabricating heterojunction bipolar... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4054414