Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
1999-12-30
2003-02-11
Picard, Leo (Department: 2125)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C700S121000, C716S030000
Reexamination Certificate
active
06519499
ABSTRACT:
BACKGROUND
An embodiment of the present invention relates to the field of analysis of defects in integrated circuits and, more particularly, to extracting likely bridge sites.
A list of bridges may be identified during defect analysis. A bridge occurs due to a point defect that extends across two or more conductive lines or nets to cause an electrical short between them.
The likelihood of occurrence of a particular bridge may be measured by its weighted critical area (WCA). The critical area for a two net bridge for a given defect size, as the term is used herein, is the area over which the center of the defect can lie and cause the two nets to bridge. The WCA of two or more nets is defined as the sum of the critical areas for a particular defect size weighted by the probability of occurrence of that defect size.
Carafe, developed at the University of California, Santa Cruz, is an example of a tool that may be used to extract potential bridges. For each layer and each adjacent layer pair in a flattened layout of an integrated circuit, Carafe generates fault primitives referred to as “length-widths.” Then, for each defect size to be analyzed, Carafe calculates corresponding critical areas from each of the length-widths. These critical areas are merged or intersected for an entire layer or layer pair to produce the critical area contribution of two-net bridges and/or multi-net bridges for the layer or layer pair for the particular defect size. The critical areas for each layer and layer pair for that defect size are then added together to find the overall critical area for the defect size. This overall critical area is then weighted with corresponding defect data to produce the WCA for the defect size. The above-described method is repeated for each defect size.
This approach has a drawback in that critical areas are computed from fault primitives for each separate defect size to be analyzed. These calculations can be time consuming, particularly where many defect sizes are used. As more defect sizes are used to more closely approximate a range of defect sizes, this inefficiency becomes even more pronounced and may preclude the use of this tool for larger or more complex layouts. Further, merging the critical areas for an entire layer or layer pair can be expensive both in terms of time and storage space on a host computer.
CREST, developed at Carnegie Mellon University, is another example of a prior fault extraction tool. CREST calculates the WCA of bridges from a hierarchical layout description. By using a hierarchical layout description instead of a flattened layout as used by Carafe, CREST may save storage space on a host computer. In doing so, however, CREST may sacrifice accuracy in computing WCA values and may fail to identify important bridges that could be identified using the flattened layout. Further, CREST currently does not identify multi-net bridges.
LOBS is another example of a prior fault extraction tool. LOBS uses a sliding window algorithm to identify critical areas. LOBS places a “window” at one corner of a layout in a layer or layer pair. A small set of rules is then used to calculate the critical area contributions from the region of the layout within the window. The window is then shifted to an adjacent area and the process is repeated until the entire layout has been covered. In using the predefined rules for calculating the critical area within the window, LOBS uses approximations when the rules are not readily applicable. These approximations can cause accuracy problems that may adversely affect the output from this tool. Further LOBS is only capable of performing two-net analysis.
Thus, the particular extraction tool used to identify likely bridges can have a significant impact on the accuracy and efficiency of the fault extraction process. Inaccurate fault extraction may compromise the quality of integrated circuit tests developed based on the output of the fault extraction. Inefficient fault extraction may take an excessive amount of time such that it is not feasible to completely analyze larger, more complex circuits.
As integrated circuits continue to increase in complexity, fault extraction using prior fault extraction tools may become increasingly difficult. Further, prior fault extraction tools may not provide the capability and/or may not be efficient enough to determine critical areas corresponding to bridges that bridge more than two nets (referred to herein as multi-net bridges).
REFERENCES:
patent: 6044208 (2000-03-01), Papadopoulou et al.
patent: 6178539 (2001-01-01), Papadopoulou et al.
patent: 6317859 (2001-11-01), Papadopoulou
Alvin Jee, David Dahle, Cyrus Baseghi and F. Joel Ferguson, Carafe User's “Manual Release Alpha.5,” http://sctest.cse.ucsc.edu/carafe/user5.html, Date Jan. 24, 1996, 18 Pages.*
E.M. McCreight, “Efficient algorithms for Enumerating Intersecting Intervals and Rectangles,” Report CSL-80-9, Xerox Palo Alto Research Center, Palo Alto, 1980.*
Alvin Jee, David Dahle, Cyrus Baseghi and F. Joel Ferguson, Carafe User's “Manual Release Alpha.5,” http://sctest.cse.ucsc.edu/carafe/user5.html, Date Jan. 24, 1996, 18 pages.
F. Preparata, M.I.Shamos, “Computational Geometry An Introduction,” Springer-Verlag, 1985, pp. 352-355.
F.M. Goncalves, I.C. Teixeria, J.P. Teixeira, “Integrated Approach for Circuit and Fault Extraction of VLSI Circuits,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Nov. 6-8, 1996, Boston Massachusetts, pp. 96-104.
F.M. Goncalves, I.C. Teixeira and J.P. Teixeira, “Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems,” IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Oct. 20-22, 1997, pp. 29-37.
Pranab K. Nag and Wojciech Maly, “Hierarchical Extraction of Critical Area for Shorts in Very Large ICs,” The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Nov. 13-15, 1995, pp. 27.
M. de Berg, M. van Kreveld, M. Overmars, O. Schwarzkopf, “Computational Geometry,” pp. 209-217, Publisher: Springer.
F. Joel Ferguson, John P. Shen, Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis, IEEE International Test Conference, 1988, pp. 475-484.
Alvin Jee and F. Joel Ferguson, “Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits,” IEEE VLSI Test Symposuim, 1992, pp. 92-98.
E.M. McCreight, “Efficient Algorithms for Enumerating Intersecting Intervals and Rectangles,” Report CSL-80-9, Xerox Palo Alto Research Center, Palo Alto, 1980.
R.E. Tarjan, “Data Structures and Network Algorithms,” Society for Industrial and Applied Mathematics, 1983.
John T. Chen, “Improved Usability of Contamination-Defect-Fault-Simulation,” Carnegie Mellon University Thesis, 1998.
J. Khare, W. Maly, “Inductive Contamination Analysis (ICA) with SRAM Application,” International Test Conference, 1995, pp. 552-560.
Chakravarty Sreejit
Roth Carl D.
Zachariah Sujit T.
Faatz Cynthia T.
Intel Corporation
Kosowski Alexander
Picard Leo
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