Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1999-03-31
2001-06-26
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S174000, C327S261000
Reexamination Certificate
active
06252445
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention pertains to the field of digital clocks. More particularly, this invention relates to a method and apparatus for extending a resolution of a clock.
2. Art Background
A wide variety of systems commonly include digital clocks. Such clocks may be used for a wide variety of timing functions in a system. One example of a timing function is to measure a time at which an event in the system occurs. Another example of a timing function is to synchronize or “trigger” an occurrence of an event at a particular time. The nature of the events depends on the particulars of the system.
In a control system, for example, the act of obtaining a data sample from a sensor is an event as is the act of applying a control value to an actuator. A digital clock may be used to measure the time at which the data sample is obtained from the sensor. In addition, a digital clock may be used to trigger the application of the control value to the actuator at a particular time.
A typical digital clock includes an oscillator and circuitry that generates digital time values in response to the oscillator. The circuitry that generates digital time values may be, for example, a counter that generates an updated time value every period or half period of the oscillator. Typically, the resolution of such a digital clock is limited by the frequency of its oscillator. For example, an oscillator that runs at 1 megahertz has a period of 1 microsecond and can generate an updated time value every 0.5 microseconds, thereby yielding a resolution of 0.5 microseconds. Such a digital clock could not reliably distinguish events that occur within 0.5 microseconds of each other and could not reliably synchronize events that are to occur within 0.5 microseconds of each other. This may limit the overall performance of the system.
One prior method of increasing the resolution of a digital clock is to increase the frequency of its oscillator. Unfortunately, an increased oscillator frequency usually increases power consumption. In addition, higher oscillator frequencies usually complicate the design of circuitry for the digital clock. Moreover, an oscillator is commonly shared with other components of a system, such as a processor, which may not be amenable to a higher oscillator frequency.
SUMMARY OF THE INVENTION
A method and apparatus is disclosed for extending a resolution of a clock in which the resolution is limited by a period of an oscillator in the clock. The present method and apparatus employs delays which are adapted to the period of the clock and which enable the determination of corrections to be applied to a timing function performed by the clock. The corrections effectively extend the resolution of the clock without increasing the frequency of the oscillator.
The present teachings may be applied to a clock in which the timing function is the measurement of a time at which an event occurs. For this timing function, a time value is obtained from the clock in response to a trigger signal for the event and then a series of values are obtained from the clock such that the time value and the series of values are delayed in time by a predetermined sub-interval of the period. A correction value to be applied to the time value is determined by detecting a pattern in the series of values.
The present teachings may also be used to extend the accuracy of a clock in which the timing function is the synchronization of signal timing. For this timing function, a trigger signal is generated when a time value from the clock equals a set of most significant bits of a trigger time value which is associated with a signal being synchronized. A set of delayed trigger signals are generated such that the trigger signal and the delayed trigger signals are spaced in time by a predetermined sub-interval of the period. A corrected trigger signal with extended resolution is selected from among the trigger signal and the delayed trigger signals in response to a set of least significant bits of the trigger time value.
Other features and advantages of the present invention will be apparent from the detailed description that follows.
REFERENCES:
patent: 5552878 (1996-09-01), Dillard
patent: 5568076 (1996-10-01), Pella et al.
Agilent Technologie,s Inc.
Le Dinh T.
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