Radiation imagery chemistry: process – composition – or product th – Including control feature responsive to a test or measurement
Reexamination Certificate
2002-06-05
2004-03-02
Young, Christopher G. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Including control feature responsive to a test or measurement
C430S022000, C430S311000
Reexamination Certificate
active
06699630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an exposure method and apparatus, and device manufacturing method. More particularly, the present invention relates to an exposure method used when a semiconductor device, liquid crystal display device, or the like is manufactured in a lithographic process, an exposure apparatus to which the exposure method is applied, and a method of manufacturing devices such as semiconductor devices and liquid crystal display devices by using the exposure method or apparatus.
2. Description of the Related Art
Conventionally, in a lithographic process for manufacturing a semiconductor device, a liquid crystal display device, or the like, an exposure apparatus has been used. In such an exposure apparatus, patterns formed on a mask or reticle (to be generically referred to as a “reticle” hereinafter) are transferred through a projection optical system onto a substrate such as a wafer or glass plate (to be referred to as a “substrate or wafer” hereinafter, as needed) coated with a resist or the like.
As apparatus of this type, a static exposure type (also called a step-and-repeat method) reduction projection exposure apparatus (a so-called stepper) and a scanning exposure apparatus based on a step-and-scan method have been put into practice. The stepper is designed to repeat stepping operations which positions a wafer stage on which a wafer as a substrate is mounted to a predetermined exposure position by moving the stage two-dimensionally by a predetermined amount. And while the wafer stage is positioned, exposing operations of transferring a reticle pattern onto a shot area on the substrate through a projection optical system is repeated. The scanning exposure apparatus is an improvement of the stepper. This apparatus is designed to synchronously move a reticle stage holding a reticle and the wafer stage in a predetermined scanning direction with respect to the projection optical system while illuminating a predetermined slit-shaped area on the reticle with an illumination light. The overall reticle pattern is transferred onto the respective shot areas on the wafer by sequentially transferring the pattern formed on the reticle in the slit-shaped area, onto the wafer through the projection optical system.
In these exposure apparatus, shot areas are arranged on a wafer at predetermined intervals in rows and columns, in a shape of a matrix (no shot areas are actually formed on the first layer, but in this case virtual shot areas are included) are exposed in a predetermined sequence. As the predetermined sequence, from the view of the moving efficiency of the wafer stage in exposure, which leads to an improvement in the throughput of the apparatus, a so-called row zigzag method or column zigzag method is generally used. In this case, the row zigzag method is a method of the exposure apparatus exposing respective shot areas arranged on the wafer in the shape of a matrix by sequentially stepping in the X direction (or in the Y direction) by a predetermined amount along a row. And on exposing the next row, the apparatus sequentially performs stepping operation in a reverse direction (parallel and reverse direction to that on the preceding row). In the column zigzag method, the “rows” in the row zigzag method are respectively replaced with “columns”, and “columns” with “rows”. Accordingly, in this specification, the terms “row zigzag method” and “column zigzag method” are hereinafter used as in the meanings described above.
On exposing the second or subsequent layers, positioning (hereinafter to be referred to as alignment) of the circuit patterns on the shot areas formed on the wafer by exposure of the preceding layer and the reticle pattern is performed. Alignment methods include the die-by-die method and the enhanced global alignment (to be referred to as “EGA” hereinafter) method which details are disclosed in U.S. Pat. No. 4,780,617. In the die-by-die method alignment is performed shot by shot. Whereas, in the EGA method the alignment marks (positioning marks transferred together with circuit patterns) are measured at a plurality of positions within the wafer. The array coordinates are then obtained of the respective shot areas by the least-squares approximation or the like, and stepping is performed by using the calculated result in accordance with the precision of the wafer stage on exposure. Of these methods, the EGA method is widely used from the aspect of throughput of the apparatus.
With the conventional exposure apparatus, on changing a shot area subject to exposure, when the first layer is exposed, the stepping amount in the row direction is determined as an integer multiple of a predetermined row interval. And the stepping amount in the column direction is set to an integer multiple of a predetermined column interval. On exposure of the second or subsequent layer that uses the EGA scheme, the stepping amount is obtained from the calculation result of the EGA.
However, determining the stepping amount conventionally by using the EGA method limited the overlay accuracy between layers. This was because the wafer gradually expanded due to irradiation thermal energy on exposure.
That is, on exposing a shot area on a layer, thermal energy is generated by the reaction of the resist coated on the wafer or by the so-called excessive optical energy which did not serve as the energy for the reaction of the resist. As a result, the wafer temperature rises. Although some of the thermal energy generated dissipates from the wafer surface into the atmosphere, most of the thermal energy stays in the wafer. The remaining thermal energy conducts through the wafer, and to the wafer holder from the rear surface of the wafer. The thermal energy is gradually conducted through the wafer reaching the holder through the lower surface of the wafer. And, the thermal energy conducted to the wafer holder circulates within the wafer holder. That is, the wafer and the wafer holder are heated together. Furthermore, since the rear surface of the holder, i.e., the opposite surface side of the surface in contact with the wafer is in contact with the wafer stage, therefore, the thermal energy is also gradually transmitted to the wafer stage.
In this process, the balance of the energy gradually moves toward the tendency in which the thermal energy is stored in the wafer and wafer holder. More specifically, the wafer and the wafer holder gradually store the thermal energy, from the beginning of exposure on the first shot area (the first shot area) on a layer until exposure of the last shot area is completed. That is, the temperature of the wafer and wafer holder gradually rise, therefore, the wafer and wafer holder gradually expand. Since the linear expansion coefficient of a Si wafer is 2.4 ppm/k, a wafer having a diameter of 20 mm expands as large as 48 nm while the temperature rises 0.1° C.
Consequently, on exposure with a conventional exposure apparatus, in general, the intervals between adjacent shot areas in a cooled state after exposure become smaller than of the designed interval as the exposure sequence proceeds. As a result, the difference between the shot area intervals in a cooled state after exposure and the designed interval lose its uniformity on the substrate. In addition, depending on the exposure sequence such as the row zigzag method or column zigzag method, the state losing its uniformity varies.
In general, on forming a semiconductor circuit, a lithographic process of 20 or more layers is required, and in each processing the overlay accuracy with its preceding layer is significant. The alignment error described above, is, naturally, a factor of this overlay error. However, even if the alignment is successfully performed, there is no guarantee that overlay between layers will be successful. This is because the reticle on which the circuit pattern is drawn and which is used to form each layer differs in transmittance and reflectance depending on the shape of the pattern drawn, and hence the energy that reaches the wafer
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