Method and apparatus for executing two types of instructions tha

Details Method and apparatus for executing two types of instructions tha Method and apparatus for executing two types of instructions tha

1995-12-19

1998-12-22

Lall, Parshotam S.

395378, 395382, 395385, 395391, 395393, 395561, 395563, 395567, 39580023, G06F 900, G06F 930

Patent

active

058527265

ABSTRACT:
A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

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