Method and apparatus for executing nested loops in a digital sig

Details Method and apparatus for executing nested loops in a digital sig Method and apparatus for executing nested loops in a digital sig

1995-12-29

1998-01-20

Lall, Parshotam S.

395568, G06F 932

Patent

active

057109133

ABSTRACT:
A digital signal processing system for executing instructions, including a program memory which stores the instructions and a program control unit for receiving and processing a sequence of the instructions to generate control signals for controlling operation of the system, and a loop circuit for use in such a program control unit. The loop circuit controls execution of a loop (preferably a nested loop) of a sequence of the instructions. Preferably, the loop circuit includes loop registers for storing loop start and end addresses and loop count values, and logic circuitry for implementing loops (including nested loops) in response to the addresses and count values in the loop registers. The loop circuit is initialized by loading appropriate addresses and values into the loop registers. After initialization, the loop circuit executes true zero overhead nested loops of instructions in the sense that the instructions to be looped need not include any initialization instructions, any special instruction to indicate the start of a loop or any dedicated branch instruction at the end of a loop for branching back to the start. Preferably, the loop circuit includes an end address comparator and circuitry for disabling this comparator when the loop circuit is not executing a loop to reduce circuit power consumption. Other aspects of the invention are methods of operating such a digital signal processor, and such a loop circuit.

REFERENCES:
patent: 4652997 (1987-03-01), Kloker
patent: 4858115 (1989-08-01), Rusterholz et al.
patent: 4862407 (1989-08-01), Fette et al.
patent: 5375238 (1994-12-01), Ooi
patent: 5481723 (1996-01-01), Harris et al.

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