Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1998-06-17
2001-08-07
Eng, David Y. (Department: 2155)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
Reexamination Certificate
active
06272616
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to digital processor architectures. More particularly, the invention pertains to the architecture of digital signal processors with multiple data paths.
DESCRIPTION OF THE PRIOR ART
There is an ever present drive to increase the power and speed of digital processors, including central processing units (CPUs) of computers and digital signal processors (DSPs). As such, many pipelined processors have architectures with multiple instruction pipelines thus allowing parallel processing of multiple instructions. In general, processor architecture designers have been relatively successful in increasing speed and power almost twofold over single pipeline processors with architecture designs having dual parallel instruction pipelines. However, obtaining correspondingly large increases in performance by further increasing the number of parallel instruction pipelines has proven to be more difficult. That is, in general, the shift from two to four parallel processors has not resulted in anything near a further twofold increase in processing speed or power.
There are several reasons for these diminishing returns. First, the limitations of typical computer codes itself makes it difficult to run more than two parallel instruction pipelines efficiently because of the dependency of subsequent instructions on the results of the execution of previous instructions (commonly termed data dependencies).
Another problem with increasing the number of parallel instruction pipelines much greater than two is that multiple instruction pipelines can create bottle necks at register file and memory ports.
There are at least three general schemes of parallelism for multiple instruction pipeline digital processors in use today. They are herein termed 1) superscalar, 2) VLIW (very long instruction word), and 3) multi-processing. Superscalar parallel processors generally use the same instruction set as single pipeline processors. The processor core includes hardware which examines a window of contiguous instructions in a program, identifies instructions within that window which can be run in parallel, and sends those subsets to different instruction pipelines in the processor core. The hardware necessary for selecting the window and parsing it into subsets of contiguous instructions which can be run in parallel is complex and consumes significant area and power. Thus, while superscalar parallelism may be practical in CPUs, its power and size requirements frequently make it unacceptable for DSP applications with stricter size and power requirements. VLIW parallelism involves the use of code comprising very long instruction words in which each VLIW actually comprises multiple instructions which are not dependent on each other and therefore can be run in parallel. In VLIW parallelism, the writer of the code or the compiler actually determines what instructions are independent and therefore can be run in parallel with each other. The code is either written or compiled to cause such independent instructions to be grouped into a VLIW. Each VLIW is parsed and then fed into multiple issue slots in the processor for execution. For example, the processor architecture might accept a sixty-four bit VLIW which actually comprises four separate individually executable sixteen bit instructions. Within the processor core, the four different sixteen bit instructions are run through four parallel instruction pipelines, each instruction pipeline including its own instruction decoder stage and execute stage.
A third method, termed multiprocessing, is the oldest and simplest of the three methods. The basic architecture of a multiprocessing system comprises two or more essentially entirely independent and parallel processors. The program writer writes the code in separate chunks which can be run independently on two different processors. Results and operands may be shared amongst the processors by writing to shared memory.
One form of multi-processing is commonly termed MIMD (multiple instructions, multiple data).
Another incarnation of parallel processing is termed SIMD (single instruction, multiple data). In SIMD type parallel processing, a single instruction is decoded and run through multiple processor pipelines wherein, in each processor pipeline, it operates on different data sets. SIMD is particularly adapted for repetitive tasks in which the same instruction is repeated many times. For instance, SIMD is particularly suitable for video data processing in which one common routine requires the contents of two sixty-four bit registers to be added to each other repetitively. In SIMD, a single instruction can be sent to eight different processing lines which can add the contents of the two 64 bit registers in eight bit chunks.
It should be apparent that the number of parallel processing threads and the type of parallelism (e.g., SIMD, MIMD, superscalar, etc.) that will most effectively increase performance is highly dependent on the particular software routine that is being executed.
U.S. Pat. No. 5,475,856 issued to Kogge discloses a dynamic multi-mode processing array that combines several of the different parallel processing concepts into a single processing array that can alternately be switched to operate in a SIMD mode, a MIMD mode or a single instruction, single data (SISD) mode during the execution of a single program. However, the device disclosed in U.S. Pat. No. 5,475,856 is adapted for use in connection with desk top computers and significantly increases power consumption and cost. The device disclosed in U.S. Pat. No. 5,475,856 is not particularly suited for the DSP environment where minimizing cost and power consumption typically are of primary concern. Specifically, the device disclosed in U.S. Pat. No. 5,475,856 includes a complex interconnection network and an extra bit in each instruction word to indicate the operational mode of each instruction pipeline.
SUMMARY OF THE INVENTION
The invention is a parallel digital processor comprising a plurality of parallel pipelined instruction paths which preferably share a common instruction memory and a common data memory. Each parallel instruction pipeline includes at least an instruction fetch stage, an instruction decoder stage and an execute stage. There are registers for each pipeline for temporarily storing data needed by, or generated as a result of, instructions. The architecture is capable of running in various modes, including single threaded mode, SIMD mode and MIMD mode. The instruction set includes instructions that cause the architecture to switch between various modes on the fly during execution of application software.
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Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading, by Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen, ACM Transactions on Computer Systems, vol. 15, No. 3, Aug. 1997, pp. 332-354.
Fernando John S.
Thurnhofer Stefan
Agere Systems Guardian Corp.
Eng David Y.
Synnestvedt & Lechner LLP
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