Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
2007-01-30
2007-01-30
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C711S212000
Reexamination Certificate
active
09536452
ABSTRACT:
Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the present invention includes a method to confine an application to an address space subset, the method including determining that the application is confined to a first bit size address subset, the application including an instruction; generating an address reference of a second bit size as part of execution of the instruction; truncating the generated address reference from the second bit size to the first bit size; and extending the truncated, generated address reference from the first bit size to the second bit size based at least in part on an address format control flag.
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Hennessy and Patterson, Computer Architecture—A Quantitative Approach, 2nd Edition, p. A-8 to A-11.
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Peleg Alexander
Ronen Ronny
Chan Eddie
Huisman David J.
Intel Corp.
Kenyon & Kenyon LLP
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