Boots – shoes – and leggings
Patent
1990-06-29
1993-10-05
Dixon, Joseph L.
Boots, shoes, and leggings
364DIG1, G06F 1300
Patent
active
052513106
ABSTRACT:
A cache memory exchange protocol that utilizes an exchange memory access request is provided A cache controller issues the exchange request over a system bus to a main memory in response to a cache miss if the cache location is dirty. Upon receiving the request, the main memory decodes the request and fetches a block of information desired by the transfers a dirty cache block of information over the system bus and stores the dirty block in a temporary register located in the main memory. The block of information desired by the CPU is thereafter transferred by the main memory to the CPU via the system bus. The dirty cache block residing in the temporary register is then stored in the main memory storage elements.
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Lidington Gary
Smelser Donald
Warchol Nicholas A.
Digital Equipment Corporation
Dixon Joseph L.
Elmore Reba I.
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