Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
2006-04-18
2006-04-18
Phan, Thai (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C703S013000, C716S030000
Reexamination Certificate
active
07031889
ABSTRACT:
A method and apparatus for evaluating the design quality of an integrated circuit design. The design to be evaluated comprises a plurality of static gates, such as, for example, NAND and NOR gates. The apparatus of the present invention comprises a computer configured to execute a rules checker program. The rules checker program analyzes each of the static gates to determine whether or not the gates meet acceptable noise immunity requirements. In order to perform this task, the rules checker program constructs models of each gate. The models emphasize or de-emphasize the strengths of certain FETs of the gate in response to noise on inputs to the gate for different logic states of the inputs. For each model, the rules checker program obtains a PFET-to-NFET width ratio. These ratios are utilized to obtain noise levels from a lookup table. Noise levels on the inputs to the gate are derived, either by calculation or simulation. These derived noise levels are then compared with the noise levels obtained from the lookup table to determine whether or not the gate being evaluated meets acceptable noise immunity requirements.
REFERENCES:
patent: 4481628 (1984-11-01), Pasquinelli
patent: 4806801 (1989-02-01), Argade et al.
patent: 5050091 (1991-09-01), Rubin
patent: 5126950 (1992-06-01), Rees et al.
patent: 5258919 (1993-11-01), Yamanouchi et al.
patent: 5325309 (1994-06-01), Halaviati et al.
patent: 5418473 (1995-05-01), Canaris
patent: 5446674 (1995-08-01), Ikeda et al.
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5586046 (1996-12-01), Feldbaumer et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5844818 (1998-12-01), Kochpatcharin et al.
patent: 5883814 (1999-03-01), Luk et al.
patent: 5936868 (1999-08-01), Hall
patent: 5987237 (1999-11-01), McBride
patent: 6055366 (2000-04-01), Le et al.
patent: 6077717 (2000-06-01), McBride
patent: 6175946 (2001-01-01), Ly et al.
patent: 6260180 (2001-07-01), McBride
patent: 6470489 (2002-10-01), Chang et al.
patent: 6499129 (2002-12-01), Srinivasan et al.
patent: 6591402 (2003-07-01), Chandra et al.
Provisional U.S. Appl. No. 60/093,830 for the US patent No. 6,499,129 B1 issued to Srinivasan et al., on Dec. 2002.
LandOfFree
Method and apparatus for evaluating the design quality of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for evaluating the design quality of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for evaluating the design quality of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3601169