Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-03-30
2003-12-16
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S081000, C716S030000
Reexamination Certificate
active
06665627
ABSTRACT:
FIELD
The present invention is directed to tester derating factor (TDF) arrangements and methodologies providing improvements in semiconductor start-to-finish manufacturing arrangements, especially within DV testing and in the world of designing of devices and virtual simulation.
BACKGROUND
Semiconductor device manufacturers often set out with a goal to design, manufacture and sell a semiconductor device which meets or provides predetermined operating characteristics, e.g., bandwidth, operating voltages, driving currents, rise/fall response times, etc. The strive toward the goal goes through at least one cycle including many stages, e.g., initially there is a virtual design stage where the device is designed virtually in computer programming and simulations (i.e., a pre-silicon stage), then there is a test production of an actual device in silicon (i.e., a post-silicon stage), followed by design validation (DV) testing of the actual post-silicon device, and finally, large volume MP and sales. While background as well as example embodiments of the present invention will be described using a pre-MP environment, uses/practice of the present invention are not limited thereto.
After virtual design and upon DV testing, DV test results often reflect that the design does not exhibit desired or expected characteristics originally designed for in the virtual design. Typically, the virtual design is then tweaked back in a design department in an attempt to adjust the device to provide desired characteristics, and then test production manufactured again and DV tested. Eventually, there is achieved a test production device with DV results having desired characteristics.
Subsequently, upon mass production, it was often found that test-run MP devices did not then provide the expected characteristics when implemented in an intended environment, e.g., when implemented on a motherboard. This often led back to further reiterations with the design department for further tweaking of the virtual design, test manufacturing, DV testing, and another test-run MP. Each reiteration of design, test manufacturing, DV testing, test-run MP and MP testing is extremely costly in terms of man hours, financial costs, and time-to-market (TtM) delays.
In order to avoid such costliness, and to minimize TtM, in the past, one technique semiconductor device manufacturers have used was to over-design semiconductor devices. For example, referencing
FIG. 3
, assume that a semiconductor manufacturer wishes to sell a semiconductor device which operates properly when operated within the range from A to B (for example, operated within a range from 33 MHz to 100 MHz). The manufacturer may then instead attempt to design the device to be operable within a broader range from C to D (e.g., operable between 10 MHz to 200 MHz), i.e., the broader ranges including a margin of error, i.e., “forgiving” ranges or tolerances. By over-designing the device, and then realizing MP via the present-day DV setups, manufacturers found that, although a good portion of the devices did not show characteristics within the broader C-D design range upon MP testing, a satisfactorily high manufacturing yield was achieved having the desired A-B characteristics. Accordingly, in the past, by including the over-designed C-A and B-D ranges within virtual design, manufacturers were advantageously allowed to finally net a high manufacturing A-B yield upon MP testing.
One disadvantage of the over-design approach is that it adds costs to production making the manufacturing process inefficient and resultant devices more costly. Further, oftentimes end users, knowing of over-design within the industry, purposely would use the device outside of the A-B characteristics range, to thereby make free use of the device's over-design without compensation to the semiconductor manufacturer. Accordingly, semiconductor manufacturer would sometimes fail to recoup the costs associated with over-design. Further, operation of the devices outside of the manufacturer's guaranteed ranges would sometimes lead to device failures and then an unfair negative effect on a reliability-reputation of the manufacturer.
The ability to over-design a device beyond desired characteristics is becoming a luxury of the past, and is becoming less available as operating frequencies of devices continue to increase. For example, when semiconductor devices were operated at lower operating frequencies (e.g., below 600 MHz), semiconductor circuits operated mainly in accordance with the basic E=IR Ohm's law without consideration to other effects. Now, with semiconductor devices designed for operation beyond such low operating frequencies (e.g., beyond 600 MHz, such as 1 GHz), other effects such as wave effects, transmission line effects, etc., come into play, such that forgiving ranges or tolerances are no longer viable. In addition, previous industry reliance on the over-design approach has led to some complacency with regard to improvements in the industry. More particularly, it has been found that there has not been adequate improvement within DV testing setups, in comparison to advances in other areas of the semiconductor device industry. Accordingly, what is needed are improvements in semiconductor start-to-finish manufacturing arrangements, and especially within DV testing, and in the world of virtual designing of devices.
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patent: 5748642 (1998-05-01), Lesmeister
patent: 6060898 (2000-05-01), Arkin
patent: 6064948 (2000-05-01), West et al.
patent: 6202030 (2001-03-01), Hitchcock
patent: 6289293 (2001-09-01), Huang
patent: 6349267 (2002-02-01), Goldthorp et al.
patent: 2002/0049554 (2002-04-01), Miller
Chema Greg P.
Jain Sunil K.
Barbee Manuel L.
Hoff Marc S.
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