Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-03-02
2002-12-10
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S711000, C438S720000, C438S729000, C438S734000, C134S001200, C216S071000
Reexamination Certificate
active
06492280
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to an improved plasma etch reactor apparatus and method.
BACKGROUND OF THE INVENTION
A new set of emerging films are being beneficially employed in the development of high density semiconductor chips such as for example high density dynamic random access memories (“DRAM”) and ferroelectric random access memories (“FRAM”). These materials provide for higher capacity devices by allowing for a reduction in the size of the individual features on the memory substrate. Accordingly, enhanced profile control technologies are required.
In the past, a number of techniques have been used to obtain a desired semiconductor feature wall profile. One technique is ion milling which is classified as a physical etching method. With this technique, an ion mill beam is used to physically sputter away portions of a layer of a semiconductor device which are not desired, leaving the desired feature defining the various components and traces on the semiconductor device. While such techniques have produced desirable profiles, the disadvantage of using ion milling techniques is that the processes are slower and such techniques tend to cause the formation of veils or fences upstanding from the desired feature.
Photoresist material is to protect and define the desired features produced by the ion milling technique. Once the photoresist material is stripped away, the veils or fences remain as undesirable and difficult to remove structures.
Chemical etching is another technique employed to remove portions of a layer of a semiconductor wafer which are unprotected by photoresist material. Such methods, while providing for faster etching than provided by, for example, ion milling, do not necessary have the same profile control afforded by ion milling.
Accordingly, there is a need to provide an etching process and apparatus which quickly and accurately processes emerging films which are used in the latest semiconductor products.
SUMMARY OF THE INVENTION
The present invention includes a method and apparatus designed to process emerging films which present unique etch problems. Such new films include for example, platinum and barium strontium titanate (BST), which are currently being used in the development of high density DRAM devices, and platinum and lead zirconium titanate (PZT) or bismuth strontium tantalate (Y−1), which are currently being used in development of non-volatile, FRAM devices. Of these new films, BST, PZT, and Y−1 have for example a high dielectric constant which allows for the development of greater circuit density, fine line geometry devices. With enhanced feature densities, more exacting vertical profile are required.
The present invention is directed to performing critical etching which results in anisotropic profiles (i.e., straight, vertical sidewalls) which is highly selective and causes minimal damage to the underlayer or other wafer materials, and which is performed uniformly over a non-uniform area.
Accordingly, the present invention provides for an apparatus and method which allows for a physical etching and then a chemical etching of a wafer in order to obtain wafer features with highly advantageous vertical sidewall profiles. The present invention provides for a method and apparatus which operates on a continuum, first emphasizing physical etching such as for example, by way of ion milling, and then emphasizing chemical etching.
Such a technique is uniquely counter-intuitive in that the ion milling portion of the process creates the desired vertical profiles, but in addition creates undesirable veils. However, advantageously, the present invention provides for a chemical etching in a continuum with the operation, which chemical etching satisfactory removes the veils. Accordingly thereafter, such that the semiconductor wafer can be operated on with other methods such as the unique rinse-strip-rinse method presented in the above U.S. patent application Ser. No. 08/438,261, now U.S. Pat. No. 5,672,239, to obtain the desired feature, configuration, densities and profiles. Thus, after the chemical etching process has occurred, the wafer is rinsed in order to remove any soluble residue prior to the stripping away of the photoresist material in a stripping or ashing step and with a subsequent post-strip rinsing of the semiconductor wafer to remove residue.
The method is performed in a chamber which has an electrode adjacent to where the semiconductor wafer is placed. The electrode is provided with a first power supply operated in the megahertz range and with a second power supply operated in the kilohertz range. During the first portion of the method, both power supplies are operable in order to enhance the ion milling technique. During the second portion of the method where the chemical etching is predominant, the second power supply operating in the kilohertz range is turned off, greatly reducing the influence of ion milling.
In another feature of the invention, a tri-electrode chamber is used wherein the bottom electrode is located adjacent the wafer and is powered as indicated above with two power supplies. A side peripheral electrode is either grounded or free-floating, and a top electrode spaced from and locked above the wafer is either grounded or allowed to be free-floating.
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Cofer Alferd
DeOrnellas Stephen P.
Rajora Paritosh
Fliesler Dubb Meyer & Lovejoy LLP
Goudreau George
Tegal Corporation
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