Excavating
Patent
1987-09-04
1989-08-15
Smith, Jerry
Excavating
364900, G06F 1110
Patent
active
048582344
ABSTRACT:
A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.
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Shu-Shia Chow; PILA Hardware Specification; 1982; pp. 1, 5-8.
Bloom Elbert
Hartwell David W.
Triolo Victoria M.
Beausoliel Robert W.
Digital Equipment Corporation
Smith Jerry
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