Method and apparatus for error measurement and reduction in a ma

Details Method and apparatus for error measurement and reduction in a ma Method and apparatus for error measurement and reduction in a ma

1988-11-23

1990-06-12

Ruggiero, Joseph

Excavating

371 28, G06F 1100

Patent

active

049339397

ABSTRACT:
An error measurement and reduction method, including the steps of inducing a high error rate in a mass storage device memory system to determine rapidly and independently the optimal pattern sensitivity, pulse pairing, and window centering error parameters for the system. In a preferred embodiment, the system error rate is then reduced by setting at least one, and preferably all three, of the error parameters to its optimal value. The inventive system includes means for performing the inventive method, and preferably includes computer-controllable means for independently adjusting the pattern sensitivity and pulse pairing error parameters associated with each read/write head of the system, and for adjusting the window centering error parameter associated with the system. The inventive method and system exploit the mutual orthogonality (with respect to overall system error rate) of the pattern sensitivity pulse pairing, and window centering error parameters, which mutual orthogonality exists when the system reads selected test patterns.

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patent: 4480274 (1984-10-01), Coleman
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patent: 4821125 (1989-04-01), Christensen
patent: 4841526 (1989-06-01), Wilson
G. Robinson, "Knowing Error Sources Lets You Evaluate Hard-Disk Drives," EDN, Feb. 5, 1987, pp. 165-170.
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"A Special Report: the TAGI Disk Test Conference," Differential Copy, Nov., 1986, pp. 5-17.
"DP8469 Synchronizer/ 2,7 ENDEC," Distributed by National Semiconductor Corporation, on or before Jun. 12, 1986, twenty-two pages.

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