Method and apparatus for error detection and correction in syste

Details Method and apparatus for error detection and correction in syste Method and apparatus for error detection and correction in syste

1984-12-20

1987-05-19

Ruggiero, Joesph

Excavating

371 38, G06F 1108, G06F 1116

Patent

active

046673261

ABSTRACT:
A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.

REFERENCES:
patent: 3896416 (1975-07-01), Barrett
patent: 4172213 (1979-10-01), Barnes
patent: 4276647 (1981-01-01), Thacker
patent: 4467373 (1984-08-01), Taylor
J. W. Clough, IBM Technical Disclosure, "Semi-Parallel Generation of CRC Character", 2/1977, pp. 3555-3556.

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