Method and apparatus for erasing memory

Details Method and apparatus for erasing memory Method and apparatus for erasing memory

2008-04-29

2008-04-29

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185330, C365S185180

Reexamination Certificate

active

11003502

ABSTRACT:
The present invention provides a method and apparatus for erasing memory blocks. The apparatus includes a first plurality of memory cells formed in a substrate and a second plurality of memory cells formed in the substrate. The apparatus further includes a bias circuit adapted to provide an erasing voltage differential to the first plurality of memory cells and a compensating voltage differential to the second plurality of memory cells, wherein the erasing voltage differential is larger than the compensating voltage differential.

REFERENCES:
patent: 6344995 (2002-02-01), Chen et al.
patent: 6344996 (2002-02-01), Tanaka et al.
patent: 6344999 (2002-02-01), Iwahashi
patent: 6345000 (2002-02-01), Wong et al.
patent: 6345367 (2002-02-01), Sinclair
patent: 6509786 (2003-01-01), Uekubo
patent: 6842380 (2005-01-01), Lakhani et al.

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