Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-05-29
2004-09-21
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S218000, C365S185300, C365S185180, C365S185250
Reexamination Certificate
active
06795348
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to a method and apparatus for erasing of a non-volatile memory device and in particular to a method and apparatus for an erase operation of a memory array of a nonvolatile memory device that can reduce the number of trapped holes in the tunnel oxide of flash memory cells.
BACKGROUND
FIG. 1
illustrates a cross sectional view of a conventional flash memory cell
100
. Memory cell
100
includes a substrate
103
, a source
104
, a control gate
108
, a floating gate
106
electrically isolated by an insulating layer of silicon dioxide (SiO
2
)
110
, and a drain
112
. Memory cell
100
is thus basically an n-channel transistor with the addition of a floating gate. Electrical access to floating gate
106
takes place only through a capacitor network of surrounding SiO
2
layers and source
104
, drain
112
, channel
105
, and control gate
108
. Any charge present on the floating gate
106
is retained due to the inherent Si—SiO
2
energy barrier height, leading to the non-volatile nature of the memory cell.
Programming a flash memory cell means that charge (i.e., electrons) is added to the floating gate
106
. A high drain to source bias voltage is applied, along with a high control gate voltage. The gate voltage inverts the channel, while the drain bias accelerates electrons towards the drain. In the process of crossing the channel, some electrons will experience a collision with the silicon lattice and become redirected towards the Si—SiO
2
interface. With the aid of the field produced by the gate voltage some of these electrons will travel across the oxide and become added to the floating gate. After programming is completed the electrons added to the floating gate increase the cell's threshold voltage. Programming is a selective operation, performed on each individual cell.
Reading a flash memory cell takes place as follows. For cells that have been programmed, the turn-on voltage V
t
of cells is increased by the increased charge on the floating gate. By applying a control gate voltage and monitoring the drain current, differences between cells with charge and cells without charge on their floating gates can be determined. A sense amplifier compares cell drain current with that of a reference cell (typically a flash cell which is programmed to the reference level during manufacturing test). An erased cell has more cell current than the reference cell and therefore is a logical “1,” while a programmed cell draws less current than the reference cell and is a logical “0.”
Erasing a flash cell means that electrons (charge) are removed from the floating gate
106
. Erasing flash memory is performed by applying electrical voltages to many cells at once so that the cells are erased in a “flash.” A typical erase operation in a flash memory may be performed by applying a positive voltage to the source
104
, a negative or a ground voltage to the control gate
108
, and holding substrate
102
of the memory cells at ground. The drain
112
is allowed to float. Under these conditions, a high electric field (8-10 MV/cm) is present between the floating gate and the source. The source junction experiences a gated-diode condition during erase and electrons that manage to tunnel through the first few angstroms of the SiO
2
are then swept into the source. After the erase has been completed, electrons have been removed from the floating gate, reducing the cell threshold voltage Vt. While programming is selective to each individual cell, erase is not, with many cells being erased simultaneously.
Stress Induced leakage current (SILC) in a flash memory occurs when there is tunneling from the floating gate through the insulating oxide surrounding it at abnormally low voltages. This can result from holes that become trapped in the tunnel oxide of the flash memory cells after the memory cell has been cycled through read, write and erase operations a number of times, i.e., “stressed,” and can severely degrade the performance of the memory. SILC presents a major challenge to designers and manufacturers of flash memory devices and will present even greater challenges as device size continues to be reduced and the insulating oxide surrounding the floating gate is made thinner.
Various solutions have been proposed to address the problem of SILC. For example, a triple well channel erase flash memory has been proposed in which a memory cell is fabricated inside a P-well that is, in turn, inside an N-well. Unfortunately, a triple well construction increases process complexity and memory area. Thus there is a need for a flash memory cell method and apparatus that reduces SILC as the device is cycled.
For the reasons stated above and for additional reasons stated hereinafter, which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved method and apparatus for erasing flash memory. The above-mentioned problems of traditional flash memories and other problems are addressed by the present invention, at least in part, and will be understood by reading and studying the following specification.
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Chen Chun
Mihnea Andrei
Leffert Jay & Polglaze P.A.
Micro)n Technology, Inc.
Nguyen Viet Q.
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