Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-11-16
2003-08-12
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000, C341S120000, C341S156000, C341S158000, C341S159000
Reexamination Certificate
active
06606048
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method and apparatus for improving the dynamic performance of multiple analog-to-digital converters (ADCs), and in particular to balancing the application of reference voltages to the ADC's comparators by coupling together the ADC's resistor ladders with at least one global line to allow current to flow therebetween, and, preferably, by applying reference voltages equally to the ADC's resistor ladders.
2. Related Art
To improve speed in analog-to-digital conversion, an interleaving technique may be adopted whereby a plurality of ADCs are coupled in parallel and timed sequentially in order to rapidly convert an incoming analog signal to an n-bit digital signal. The more ADCs that are coupled together, the faster the overall output. While speed is thus improved, accuracy may suffer due to the variations between the ADCs in, for example, gain, offset, timing, frequency/phase response, non-linearity, etc. These variations often result from minor manufacturing differences between the ADCs, and such differences become more pronounced as the dimensions of the ADCs decrease. U.S. Pat. No. 4,968,988 (incorporated herein by reference) addresses this problem by providing a plurality of ADC sub-converters monolithically integrated in one array and sequentially activated in a time-interleaved fashion. ADC sub-converters in proximity to each other are activated in an attempt to minimize manufacturing differences to improve the differential linearity. However, ADC-to-ADC variations still exist, leading to relatively poor dynamic performance.
U.S. Pat. No. 5,239,299 (incorporated herein by reference) discloses an equalizing method for compensating ADC-to-ADC variations, by designation one of the ADCs as a reference ADC. Individual characteristics of the remaining ADCs are compared with the reference ADC to provide differential responses thereto. These differential responses are then equalized to provide compensation for variations in gain, offset, etc. However, such comparison and equalization circuitry requires additional space and introduces yet another source of variations which introduce further inaccuracies.
Thus, what is needed is a simpler, multiple-ADC design (capable of monolithic integration) which will greatly reduce ADC-to-ADC variations and improve dynamic performance.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the problems described above, and to provide a multiple ADC design which equalizes ADC performance by ensuring that substantially equal reference voltages are applied to the comparators of each ADC.
In a first aspect of the present invention, equalizing first and second ADCs (which have corresponding first and second resistor strings) includes structure and/or steps whereby a positive reference voltage terminal is disposed substantially halfway between the first resistor string and the second resistor string. A negative reference voltage terminal is disposed substantially halfway between the first resistor string and the second resistor string, and a global line couples together the first resistor string and the second resistor string at a point spaced from both the positive reference voltage terminal and the negative reference voltage terminal.
According to another aspect of the present invention, ADC apparatus includes a first ADC having a first decoder, a first plurality of comparators, a first switching circuit, a first RAM, and a first resistor ladder. A second ADC is provided and has a second decoder, a second plurality of comparators, a second switching circuit, a second RAM, and a second resistor ladder. Positive voltage wiring is coupled to first ends of the first and second resistor ladders, and negative voltage wiring is coupled to second ends of the first and second resistor ladders. A positive reference terminal is disposed at a midpoint of the positive voltage wiring, and a negative voltage terminal is disposed at a midpoint of the negative voltage line. A global line is coupled between the first and second resistor ladders and tends to equalize current flowing in the first and second resistor ladders.
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Harness & Dickey & Pierce P.L.C.
Janofsky Eric B.
Marvell International Ltd.
Nguyen Linh V
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