Method and apparatus for ensuring synchronization of clocks...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S142000

Reexamination Certificate

active

07084679

ABSTRACT:
An apparatus, a method, and a computer program product are provided for producing a synchronous divider reset signal. A notorious concern with multiple non-integer frequency ratio synchronous source clocks has been the time of edge alignment between the respective clocks. To address this concern, a number of latches can be utilized in order to detect alignment of the edges of these clocks. Specifically, the latches are employed to assist in the production of a synchronous divider reset signal for downstream dividers that are utilized in many microprocessors today. Hence, all of the downstream dividers can be properly synchronized to alleviate any errors that can occur between respective macros of a microprocessor chip resulting from misalignment of clock edges.

REFERENCES:
patent: 4689764 (1987-08-01), Daniels
patent: 5086387 (1992-02-01), Arroyo et al.
patent: 5726593 (1998-03-01), Ruuskanen
patent: 6175603 (2001-01-01), Chapman et al.
patent: 6473476 (2002-10-01), Banks
patent: 6900674 (2005-05-01), Sutera et al.

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