Method and apparatus for enhancing performance of design verific

Details Method and apparatus for enhancing performance of design verific Method and apparatus for enhancing performance of design verific

1996-04-05

1998-09-22

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364489, 364491, G06F 1750

Patent

active

058124152

ABSTRACT:
A method implemented on a computer system for enhancing performance of an integrated circuit design verification system, the computer system having a memory including a circuit design, the circuit design including a base layer, a first layer, a second layer, a first derived layer, and a second derived layer, the first derived layer defined in response to operation between the base layer and the first layer, the second derived layer defined in response to an operation between the second layer and the first derived layer, includes the steps of retrieving the first layer from the memory, the first layer located within the base layer, deriving a negative first derived layer in response to the first layer, the negative first derived layer being a negative domain representation of the first derived layer, and verifying the circuit design in response to the negative first derived layer.

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