Method and apparatus for enhanced timing loop for a PRML...

Details Method and apparatus for enhanced timing loop for a PRML... Method and apparatus for enhanced timing loop for a PRML...

2005-04-12

2005-04-12

Ha, Dac V. (Department: 2634)

Pulse or digital communications

Equalizers

Automatic

C375S327000, C375S355000, C375S362000, C370S503000, C348S537000

Reexamination Certificate

active

06879629

ABSTRACT:
Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state. The selector function utilizes the low latency detector output and selects the state of the path memory. The selector function provides a low latency output corresponding to the selected state. The low latency output is used for generating the timing error signal during a read operation.

REFERENCES:
patent: 4890299 (1989-12-01), Dolivo et al.
patent: 5258933 (1993-11-01), Johnson et al.
patent: 5384671 (1995-01-01), Fisher
patent: 5416806 (1995-05-01), Coker et al.
patent: 5426541 (1995-06-01), Coker et al.
patent: 5552942 (1996-09-01), Ziperovich et al.
patent: 5754352 (1998-05-01), Behrens et al.
patent: 5841664 (1998-11-01), Cai et al.
patent: 5959837 (1999-09-01), Yu
patent: 6587529 (2003-07-01), Staszewski et al.
patent: 0 701 255 (1996-03-01), None

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