Coded data generation or conversion – Digital code to digital code converters – To or from run length limited codes
Reexamination Certificate
2003-04-08
2004-07-20
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from run length limited codes
C341S058000
Reexamination Certificate
active
06765511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of encoding digital data. In addition, this invention relates to an apparatus for encoding digital data. Furthermore, this invention relates to a recording medium, a transmission medium, and a computer-related program.
2. Description of the Related Art
Some encoding (modulation) systems used for digital signals recorded on recording mediums are of an RLL(d, k) type, where “RLL(d, k)” means run length limiting rules such that “d” to “k” successive bits of “0” should be between bits of “1” in an encoding-resultant bit stream.
General systems for encoding first digital signals into second digital signals which follow RLL(d, k) include a block encoding system and a variable-length encoding system. A typical example of the block encoding system is an EFMPlus (eight-to-sixteen modulation) system for digital versatile discs (DVDs). A typical example of the variable-length encoding system is one used for magnetic recording which conforms to RLL (1, 7).
The EFMPlus system encodes every 8-bit block of digital data into a 16-bit code word by referring to an encoding table, and serially connects the resultant code words to get a code-word sequence in the form of a bit stream which satisfies RLL(d, k). Thus, the EFMPlus system implements conversion from 8 bits to 16 bits.
Basically, the variable-length encoding system for magnetic recording converts a 2-bit input data piece into a 3-bit output code word. Sometimes, the variable-length encoding system converts a 4-bit or 6-bit input data piece into a 6-bit or 9-bit output code word. Thus, the data conversion by the variable-length encoding system relates to an encoding constraint length changeable among three different values. The variable-length encoding system serially connects the resultant output code words to get an output code-word sequence in the form of a bit stream. One is selected among the conversion from 2 bits to 3 bits, the conversion from 4 bits to 6 bits, and the conversion from 6 bits to 9 bits in response to a bit pattern of the input data so that the output code-word sequence will follow RLL(d, k).
Japanese patent application publication number 11-346154/1999 discloses an RLL(1, 7) modulation apparatus which includes an inserting section for adding DSV (digital sum value or digital sum variation) control bits to an input data sequence. The inserting section outputs the DSV-control-bit-added data to a modulator. The modulator handles the output data from the inserting section as data having a basic data length of 2 bits. According to conversion tables, the modulator converts the output data from the inserting section into data of a variable length code having a basic data length of 3 bits. The modulator outputs the variable-length-code data to an NRZI converter. The conversion tables have a replacement code for restricting succession of a minimum run to a prescribed number of times or less, and a replacement code for observing the run length limiting rules. The conversion tables further have a conversion rule such that the remainder in the division of the number of bits of “1” in each input element by 2 and the remainder in the division of the number of bits of “1” in a corresponding output element by 2 are equal to each other as 1 or 0. Thus, each input element and a corresponding output element are equal in polarity (“odd-even” in the number of bits of “1” in an element). The modulation apparatus in Japanese application 11-346154 implements DSV control while forcing the modulation-resultant (conversion-resultant) bit stream to follow RLL(1, 7).
In Japanese application 11-346154, the modulator encodes a 2-bit, 4-bit, 6-bit, or 8-bit input data piece into a 3-bit, 6-bit, 9-bit, or 12-bit output code word by referring to the conversion tables. The encoding is of the variable length type. The conversion tables are based on the following assignment of input data pieces to output code words.
input data piece
output data piece
11
*0*
10
001
01
010
0011
010 100
0010
010 000
0001
000 100
000011
000 100 100
000010
000 100 000
000001
010 100 100
000000
010 100 000
″110111
001 000 000 (next 010)
00001000
000 100 100 100
00000000
010 100 100 100
if xx1 then *0* = 000
if xx0 then *0* = 101
The above-indicated 2-bit input data pieces correspond to a constraint length of “1”. The above-indicated 4-bit input data pieces correspond to a constraint length of “2”. The above-indicated 6-bit input data pieces correspond to a constraint length of “3”. The above-indicated 8-bit input data pieces correspond to a constraint length of “4”.
The modulation apparatus in Japanese application 11-346154 includes a portion for deciding which of constraint lengths a current input data piece corresponds to, and also a portion for minimum-run detection control. Therefore, the modulation apparatus is complicated in structure.
SUMMARY OF THE INVENTION
It is a first object of this invention to provide a relatively simple method of encoding digital data.
It is a second object of this invention to provide a relatively simple apparatus for encoding digital data.
It is a third object of this invention to provide an improved recording medium.
It is a fourth object of this invention to provide an improved transmission medium.
It is a fifth object of this invention to provide an improved computer-related program.
A first aspect of this invention provides a method of encoding an input bit stream into a stream of output code words according to variable-length encoding rules using a variable constraint length. A maximum value N of the constraint length is equal to or greater than 2, and the output-code-word stream observes prescribed run length limiting rules RLL(d, k), where “d” and “k” denote a predetermined minimum run length and a predetermined maximum run length respectively. The method comprises the steps of encoding every m-bit piece of the input bit stream into an n-bit output code word by referring to predetermined M encoding tables following the variable-length encoding rules, “m” and “n” denoting predetermined natural numbers respectively, M denoting a predetermined natural number equal to or greater than 2; generating CDS (code word digital sum) values corresponding to respective n-bit output code words generated by the encoding step; generating DSV (digital sum variation) control bits in response to the generated CDS values; periodically inserting the generated DSV control bits into the input bit stream at intervals each corresponding to a prescribed number of successive bits; and subjecting the input bit stream to variable-length encoding while implementing DSV control responsive to the inserted DSV control bits.
A second aspect of this invention is based on the first aspect thereof, and provides a method further comprising the steps of calculating DSV values equal to accumulations of the CDS values; deciding the DSV control bits in response to the calculated DSV values; and subjecting the input bit stream to the variable-length encoding in accordance with the M encoding tables.
A third aspect of this invention is based on the first aspect thereof, and provides a method wherein the numbers “d” and “k” are equal to 1 and 7, respectively.
A fourth aspect of this invention provides an apparatus for encoding an input bit stream into a stream of output code words according to variable-length encoding rules using a variable constraint length. A maximum value N of the constraint length is equal to or greater than 2, and the output-code-word stream observes prescribed run length limiting rules RLL(d, k), where “d” and “k” denote a predetermined minimum run length and a predetermined maximum run length respectively. The apparatus comprises first means for encoding every m-bit piece of the input bit stream into an n-bit output code word by referring to predetermined M encoding tables following the variable-length encoding rules, “m” and “n” denoting predetermined natural numbers respectively, M denoting a predetermined natural number equal to or greater than
Jean-Pierre Peguy
Victor Company of Japan Ltd.
Woo Louis
LandOfFree
Method and apparatus for encoding digital data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for encoding digital data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for encoding digital data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3224549