Data processing: structural design – modeling – simulation – and em – Emulation
Reexamination Certificate
2008-04-08
2008-04-08
Thangavelu, K. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
C703S028000, C703S025000, C703S016000, C716S030000, C716S030000, C714S710000
Reexamination Certificate
active
07356454
ABSTRACT:
A method for emulating a logic circuit having at least one set of identical logic modules is disclosed. Each logic module in a set has logic elements and memory elements that store a module state of that logic module. The logic circuit is emulated by extracting a logic module from a set of identical logic modules, translating the extracted logic module for iterative representation of the module state of each of the logic modules with a single instance of the logic elements, and configuring a logic device with the translated logic module to emulate the logic circuit.
REFERENCES:
patent: 5309444 (1994-05-01), Dartois et al.
patent: 5551013 (1996-08-01), Beausoleil et al.
patent: 5581742 (1996-12-01), Lin et al.
patent: 5596742 (1997-01-01), Agarwal et al.
patent: 5841967 (1998-11-01), Sample et al.
patent: 5850537 (1998-12-01), Selvidge et al.
patent: 5872953 (1999-02-01), Bailey
patent: 5960191 (1999-09-01), Sample et al.
patent: 6298319 (2001-10-01), Heile et al.
patent: 6377911 (2002-04-01), Sample et al.
patent: 6377912 (2002-04-01), Sample et al.
patent: 6404224 (2002-06-01), Azegamie et al.
patent: 6618698 (2003-09-01), Beausoleil et al.
patent: 7130787 (2006-10-01), Noury et al.
patent: 2002/0161568 (2002-10-01), Sample et al.
patent: 2003/0212539 (2003-11-01), Beausoleil et al.
patent: 101 42 553 (2003-04-01), None
Young et al., “Generation of universal series-parallel Boolean functions”, ACM 1999.
Gao Guang R.
Karna Vishal
Leung Clement
Sakane Hirofumi
Yakay Levent
RatnerPrestia
Thangavelu K.
UD Technology Corporation
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