Patent
1996-09-25
1998-06-30
Teska, Kevin J.
395376, 395379, 395385, G06F 9455, G06F 9302, G06F 9305
Patent
active
057746940
ABSTRACT:
A method and apparatus for emulating status flags on a computer system that has no native support for status flags. One embodiment of the invention includes decoding an arithmetic instruction executable on a first Instruction Set Architecture (ISA), wherein the instructions generates at least one status flag when executed on the first ISA. The arithmetic instruction is translated to be executable on a second ISA. When executed on the second ISA, the translated arithmetic instruction generates a first intermediate result by performing a first logical exclusive-or (XOR) operation between a first operand and a second operand. The arithmetic instruction then generates a first final result by performing a second XOR operation between the first intermediate result and an arithmetic result, which was generated by an arithmetic operation specified by the arithmetic instruction. As a result, the first final result has at least one bit representing a status flag of the arithmetic result.
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Frejd Russell W.
Intel Corporation
Teska Kevin J.
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