Method and apparatus for emulating a processor

Data processing: structural design – modeling – simulation – and em – Emulation – In-circuit emulator

Reexamination Certificate

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Reexamination Certificate

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07072824

ABSTRACT:
One or more processor operations are emulated in a programmable logic device (PLD) (205) that selectively mimics processor behavior by a program that downloads (505) one or more processor operations into the PLD (205). Each operation may be selected (501) and repeated (513) continuously without interruption from any other processor operation unless such interruption is desired to take place. In addition, the PLD (205) has an adjustable or variable clock speed that provides for the ability to select (507) and change (511) the clock speed under which the test circuit is exercised.

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Lewis, David M.; Galloway, David R.; van Ierssel, Marcus; Rose, Jonathan; Chow, Paul; “The Transmogrifier-2: A 1 Million Gate Rapid-Prototyping System”, Jun. 1998, IEEE Transactions on Very Large Scale Integration Systems.
“Flex 10K Device Family”, Mar. 2000, web.archive.org/web/20000303160208/www.altera.com/html/products/f10k.html.
Wray, William C.; Greenfield, Joseph D; “Using microprocessors and microcomputers: the Motorola family”, 1994, Prentice-Hall.
Brynjolfson, Ian; Zilic, Zeljiko; “Dynamic Clock Management for Low Power Applications in FPGAs”, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, May 21-24, 2000 pp. 139-142.

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