Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
1999-02-01
2002-04-30
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S284000, C327S295000, C327S415000
Reexamination Certificate
active
06380785
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to digital test circuitry, and more particularly to a method and apparatus for eliminating shoot-through events during master-slave flip-flop scan operations while incorporating minimal test time.
BACKGROUND OF THE INVENTION
The testing of electrical circuits is an essential portion of the process involved in the design and manufacture of electrical circuits. One testing technique often employed in the testing of electrical circuits is the use of a test access port (TAP). The use of a TAP allows signals to be serially scanned in and out of an integrated circuit (IC) to test the circuit for functional defects. The TAP architecture is well known in the art and has been defined in an Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1-1990.
FIG. 1
is a block diagram of a typical prior art integrated circuit (IC)
100
containing TAP circuitry
120
. Dedicated TAP pins TDI
112
, TCK
114
, TDO
116
, and TMS
118
are provided to allow communication from an external tester to a set of internal scan registers
160
a
,
160
b
, . . . ,
160
n
, and
108
. Test Clock (TCK) pin
114
and Test Mode Select (TMS) pin
118
are both coupled to a Test Access Port (TAP) controller
130
, and are used to implement a communication protocol, preferably the “JTAG” (Joint Test Action Group) protocol which is described in detail in the IEEE/ANSI Standard 1149.1-1990.
IC
100
includes internal logic
106
that is coupled to receive input data via input pins
102
and to output output data via output pins
104
. Internal registers and/or test nodes of interest are coupled to internal scan chains
160
a
,
160
b
, . . . ,
160
n
. Each scan chain
160
a
,
160
b
, . . . ,
160
n
comprises one or more scan chain cells
110
. Each scan chain cell
110
is typically implemented using a master-slave flip-flop. In the illustrative embodiment, IC
100
also includes a boundary scan chain
108
. Boundary scan testing is a well-known testing technique in which each IC component that is part of a larger circuit under test is constructed with a set of shift registers placed between each device pin and the component's specific internal logic system and which allows an entire circuit to be accurately tested by scanning only the boundary pins of the components of the circuit under test. In the illustrative embodiment, each input pin
102
and output pin
104
of interest is coupled to a separate boundary scan chain cell
110
, which are coupled serially in a loop configuration to form boundary scan register
108
. At any given time, Test Data In (TDI) pin
112
and Test Data Out (TDO) pin
116
are each switchably coupled to one of the instruction register
140
, one of the internal scan registers
160
a
,
160
b
, . . . ,
160
n
, or boundary scan register
108
.
TAP instruction register
140
is used to set the mode of operation of the TAP
120
. In operation, instructions are loaded into instruction register
140
under the control of TMS pin
118
and TCK pin
114
via TDI pin
112
. The instruction present in instruction register
140
determines which one of the instruction register
140
, one of the internal scan registers
160
a
,
160
b
, . . . ,
160
n
, or boundary scan register
108
, is coupled between the TDI pin
112
and TDO pin
116
. Data is shifted serially into the currently selected register
140
,
160
a
,
160
b
, . . . ,
160
n
, or
108
via TDI pin
112
in synchronization with a clock signal received on TCK pin
114
.
Scan chain cells
110
are latches, typically implemented with a master-slave flip-flop, illustrated at
200
in FIG.
2
(
a
). When scanning serial data into master-slave flip-flops
200
, data movement takes place on each edge of the test clock TCK (shown in accompanying FIG.
2
(
b
)). This movement takes place upon assertion of two signals generated by the TAP from the test clock signal TCK—master clock TCKM and slave clock TCKS. By IEEE 1149.1 specifications, data is required to be shifted on the falling edge of test clock TCK. When master clock TCKM is asserted, serial data is loaded one bit at a time from the input
211
of the flip-flop
200
into the master latch
210
of each flip-flop
200
. When the slave clock TCKS is asserted, data stored in each master latch
210
is copied into its respective slave latch
220
and driven from the output S_OUT
225
of the slave latch
220
to the input M_IN
211
of the master latch
210
of the next boundary scan chain cell
110
in the scan chain
108
.
Care must be taken when designing this test circuitry. If at any moment the master clock TCKM and slave clock TCKS are both above the trip-point, shown at “T” for signals TCKM and TCKS in FIG.
2
(
b
), of the latch enable gates
212
,
222
, data will “shoot-through” multiple scan chain cell latches
110
in the scan chain
160
a
,
160
b
, . . . ,
160
n
,
108
, corrupting the previously-stored scan data. For this reason, most test circuitry implements delay-generating logic between the master and slave clock signal lines to ensure that the master clock TCKM and slave clock TCKS do not overlap. The time when neither master clock TCKM or slave clock TCKS is asserted is commonly referred to as “dead-time”. This is illustrated in FIG.
2
(
b
). If an excessive amount of dead-time is introduced between the master and slave clock signals TCKM and TCKS, the test clock TCK frequency must be decreased, increasing the amount of test time per circuit under test. This can be very expensive on high-volume manufacturing test lines.
Shoot-through problems occur more frequently when the load on the master and slave clock signals TCKM and TCKS is high, as often is the case when driving long scan chains.
Prior art solutions to shoot-through problems introduce by excessive loading on the master and slave clock lines include introducing a fixed delay between the master clock TCKM and slave clock TCKS. However, this solution is problematic if the fixed delay is set to introduce too large of an amount of dead-time between the master and slave clocks since the frequency of the test clock TCK is forced to be slower. The slower test clock frequency increases the amount of test time and thus the cost of the test. If the delay value is set too low, shoot-through conditions will occur in the scan chains where loading mismatches occur.
Another prior art solution involves the use of test module satellites. This method requires the installation of test modules, which buffer the test signals from the TAP and generate the non-overlapping clocks local to each block. This method greatly reduces the risk of shoot-through, but requires that test modules be generated, sized correctly, verified, and placed in each block of the circuit, increasing both design time and overall area of the chip.
Another solution to the problem is the use of long-route feedback. In this method an output signal from the TAP is routed around the periphery of the integrated circuit and returned as an input to the TAP. This delay introduced by the long trace represents a fixed delay which acts as the dead-time between the master and slave clock signals TCKM and TCKS of the TAP. The disadvantage of the implementation is two-fold. First, if the delay is too long, tester time is unnecessarily increased; if the delay is too short, shoot-through is introduced. Second, the long trace inherits large inductive properties due to its loop-like nature. The trace must therefore carry extra width, taking up more area on the chip. Since the trace also exists in the outer-most part of the core, extra care must be taken that the top-level router does not route on top of the trace. If the long-route is hand-placed after the top-level route, highly congested areas of the chip will be difficult to pass through.
Each of the prior art solutions to shoot-through problems in master-slave latches results in other problems as described above. Accordingly, a need exists for a method and apparatus which allows a test engineer to calibrate the amount of dead-time, t
Agilent Technologie,s Inc.
Callahan Timothy P.
Neudeck Alexander
Nguyen Minh
LandOfFree
Method and apparatus for eliminating shoot-through events... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for eliminating shoot-through events..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for eliminating shoot-through events... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2859263