Patent
1995-07-28
1997-12-23
Butler, Dennis M.
395309, G06F 112
Patent
active
057014477
ABSTRACT:
An alignment unit is provided for aligning signals transmitted between a core clock domain and a bus clock domain. The alignment unit includes at least one alignment latch connected along each signal path between the core and bus clock domains. For critical path signal lines, the alignment unit also includes a latch bypass to allow critical signals to bypass the latch in circumstances when the core and bus clock signals are already aligned. The bypass mechanism includes a multiplexer which transmits the critical path signal through a tristate buffer if the clock signals are aligned or through a latch and a tristate buffer if the clock signals are unaligned. By bypassing the latch when the signals are aligned, latch propagation delays are avoided. Method and apparatus embodiments are disclosed.
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Butler Dennis M.
Intel Corporation
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