Static information storage and retrieval – Addressing – Byte or page addressing
Reexamination Certificate
2000-08-31
2001-10-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Byte or page addressing
C365S194000, C365S200000
Reexamination Certificate
active
06298007
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to memory devices. More particularly, the present invention relates to a method and apparatus for eliminating false data in a page mode memory device.
Design goals for memory devices such as semiconductor memories include high speed, low read time and write time, large capacity, minimized power dissipation and minimal cost. Satisfaction of these goals typically requires trade-off. For example, a low read time and write time are harder to achieve in a large capacity memory because of internal capacitances and current drive limitations of the transistors used in the memory.
Semiconductor memory devices have been developed in a variety of technologies to provide particular features for a user. Generally, semiconductor memories may be classified as volatile and nonvolatile. Volatile memories do not retain stored data when operating power is removed. Examples are random access memory (RAM). Nonvolatile memories do retain stored data even when power is removed. Examples include electrically programmable read only memory (EPROM) and flash memory. Nonvolatile memories store charge on an insulated floating gate of a core cell to change the threshold voltage of an associated transistor. The threshold voltage is indicative of the data stored in the core cell.
In addition to memory technology, memory architectures have been developed to enhance memory performance. One example of a memory architecture is a page mode memory. In a page mode memory operated in page mode, a plurality of words on a common page are sensed at one time. By changing a word address applied to the memory, different words of data may be provided at the output. The sensing and output time is relatively long, for example, 115 ns. However, once the data have been sensed and the first word provided at the output, providing subsequent words from the page takes much less time, such as 25 ns. Thus, page mode memories allow multiple words to be read at a higher average access time.
To reduce the manufacturing cost of a memory, it is known to include redundant elements such as core cells and sense amplifiers, which detect the state of associated core cells. During testing of the memory, faulty core cells and sense amplifiers are detected and replaced with redundant elements. Use of redundant elements improves the overall manufacturing yield and therefore reduces the manufacturing cost for each memory.
Some page mode memories employing redundant elements have exhibited a false data problem. After an initial page mode access is made, the data is sensed from core cells of the memory, then latched and sent to the output buffers and input/output pads of the memory. The data is latched so that subsequent word accesses need only select the latched word data, rather than having to access the core cells where the data is stored. Subsequent word accesses occur by asserting a word address and generating word decode signals to select the proper latched data. If the word decode signals occur before the latch containing the data is set, then the data in process of being modified in the latch will propagate to the output. That is old data will propagate to the output rather than the newly sensed data.
This false data propagation causes several problems. First, the incorrect or false data may be inadvertently detected by the circuit which is accessing the memory, creating an error in subsequent processing. Second, to reduce such errors may require slowing down the operation of the memory. Specifically, the page mode read access time may be increased. In one implementation, it has been observed that the problem occurs mainly in two cases. First, the problem occurs when switching between redundant blocks, which causes the word decode signals of the previous block to give false data for the new block. Second, the problem occurs when inside a redundancy block while switching between a regular element to a redundant element.
Since these problems are undesirable, there is a need for a method and apparatus for eliminating false data in a page mode memory device.
BRIEF SUMMARY OF THE INVENTION
By way of introduction only, a method and apparatus in accordance with the present invention uses address transition detection to delay word decode signals. The address transition signals are delayed to produce a control signal. The control signal controls the flow of data from the regular or redundant sense amplifiers to the output buffers. This control signal allows the correct data to reach the memory outputs and prevents any false data transitions.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation of the following claims, which define the scope of the invention.
REFERENCES:
patent: 5289413 (1994-02-01), Tsuchida et al.
patent: 5757703 (1998-05-01), Merritt et al.
patent: 6111814 (2000-08-01), Schaefer
Kasa Yasushi
Santurkar Vikram S.
Advanced Micro Device Inc.
Le Thong
Nelms David
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